This paper presents a 12-channel,30Gb/s front-end amplifier realized in standard 0.18μm CMOS technology for parallel optlc-fiber receivers. In order to overcome the problem of inadequate bandwidth caused by the large...This paper presents a 12-channel,30Gb/s front-end amplifier realized in standard 0.18μm CMOS technology for parallel optlc-fiber receivers. In order to overcome the problem of inadequate bandwidth caused by the large parasitical capacitor of CMOS photo-detectors,a regulated-cascode structure and noise optimization are used in the design of the transimpedance amplifier. The experimental results indicate that, with a parasitical capacitance of 2pF,a single channel is able to work at bite rates of up to 2.5Gb/s,and a clear eye diagram is obtained with a 0. 8mVpp input. Furthermore, an isolation structure combined with a p^＋ guard.ring （PGR）, an n^＋ guard-ring （NGR）,and a deep-n-well （DNW） for parallel amplifier is also presented. Taking this combined structure, the crosstalk and the substrate noise coupling have been effectively reduced. Compared with the isolation of PGR or PGR ＋ NGR,the measured results show that the isolation degree of this structure is improved by 29.2 and 8. ldB at 1GHz,and by 8. 1 and 2. 5dB at 2GHz,respectively. With a 1.8V supply,each channel of the front-end amplifier consumes a DC power of 85mW,and the total power consumption of 12 channels is about 1W.展开更多
A 1.8-V 64-kb four-way set-associative CMOS cache memory implemented by 0.18μm/1.8V 1P6M logic CMOS technology for a super performance 32-b RISC microprocessor is presented.For comparison,a conventional parallel acce...A 1.8-V 64-kb four-way set-associative CMOS cache memory implemented by 0.18μm/1.8V 1P6M logic CMOS technology for a super performance 32-b RISC microprocessor is presented.For comparison,a conventional parallel access cache with the same storage and organization is also designed and simulated using the same technology.Simulation results indicate that by using sequential access,power reduction of 26% on a cache hit and 35% on a cache miss is achieved.High-speed approaches including modified current-mode sense amplifier and split dynamic tag comparators are adopted to achieve fast data access.Simulation results indicate that a typical clock to data access of 2.7ns is achieved...展开更多
文摘This paper presents a 12-channel,30Gb/s front-end amplifier realized in standard 0.18μm CMOS technology for parallel optlc-fiber receivers. In order to overcome the problem of inadequate bandwidth caused by the large parasitical capacitor of CMOS photo-detectors,a regulated-cascode structure and noise optimization are used in the design of the transimpedance amplifier. The experimental results indicate that, with a parasitical capacitance of 2pF,a single channel is able to work at bite rates of up to 2.5Gb/s,and a clear eye diagram is obtained with a 0. 8mVpp input. Furthermore, an isolation structure combined with a p^＋ guard.ring （PGR）, an n^＋ guard-ring （NGR）,and a deep-n-well （DNW） for parallel amplifier is also presented. Taking this combined structure, the crosstalk and the substrate noise coupling have been effectively reduced. Compared with the isolation of PGR or PGR ＋ NGR,the measured results show that the isolation degree of this structure is improved by 29.2 and 8. ldB at 1GHz,and by 8. 1 and 2. 5dB at 2GHz,respectively. With a 1.8V supply,each channel of the front-end amplifier consumes a DC power of 85mW,and the total power consumption of 12 channels is about 1W.
文摘A 1.8-V 64-kb four-way set-associative CMOS cache memory implemented by 0.18μm/1.8V 1P6M logic CMOS technology for a super performance 32-b RISC microprocessor is presented.For comparison,a conventional parallel access cache with the same storage and organization is also designed and simulated using the same technology.Simulation results indicate that by using sequential access,power reduction of 26% on a cache hit and 35% on a cache miss is achieved.High-speed approaches including modified current-mode sense amplifier and split dynamic tag comparators are adopted to achieve fast data access.Simulation results indicate that a typical clock to data access of 2.7ns is achieved...
