An efficient parallel global router using random optimization that is independent of net ordering is proposed.Parallel approaches are described and strategies guaranteeing the routing quality are discussed.The wire le...An efficient parallel global router using random optimization that is independent of net ordering is proposed.Parallel approaches are described and strategies guaranteeing the routing quality are discussed.The wire length model is implemented on multiprocessor,which enables the algorithm to approach feasibility of large scale problems.Timing driven model on multiprocessor and wire length model on distributed processors are also presented.The parallel algorithm greatly reduces the run time of routing.The experimental results show good speedups with no degradation of the routing quality.展开更多
To keep even current distribution among DC/DC converters in a paralleled power system,an automatic master-slave control （AMSC） current sharing scheme is presented,which was implemented by a current share control IC....To keep even current distribution among DC/DC converters in a paralleled power system,an automatic master-slave control （AMSC） current sharing scheme is presented,which was implemented by a current share control IC. A current feedback loop for output voltage adjustment is proposed for low signal distortion. Moreover,a special startup control logic is designed to improve startup timing and to speed up the initial current sharing. It was completed in 1.5μm bipolar-CMOS-DMOS （BCD） technology with an area of 3.6mm^2 . Using it,a paralleled power system of two DC/DC converters capable of outputting 12V/3A was built. Experimental results show that the current sharing error at full load is kept within 1%.展开更多
A novel numerical algorithm of fault location estimation for four-line fault without ground connection involving phases from each of the parallel lines is presented in this paper. It is based on one-terminal voltage a...A novel numerical algorithm of fault location estimation for four-line fault without ground connection involving phases from each of the parallel lines is presented in this paper. It is based on one-terminal voltage and current data. The loop and nodal equations comparing faulted phase to non-faulted phase of two-parallel lines are introduced in the fault location estimation model, in which the source impedance of a remote end is not involved. The effects of load flow and fault resistance on the accuracy of fault location are effectively eliminated, therefore a precise algorithm of locating fault is derived. The algorithm is demonstrated by digital computer simulations.展开更多
In this paper,the cause of bit-error is analyzed when data are decided in the optical receiver.A monolithic D-ff decision circuit is designed.It can work effectively at 622 Mb/s.Moreover,a decision method of parallel ...In this paper,the cause of bit-error is analyzed when data are decided in the optical receiver.A monolithic D-ff decision circuit is designed.It can work effectively at 622 Mb/s.Moreover,a decision method of parallel processing to improve the decision speed is presented,through which the parallel circuit can work up to 1 Gb/s using the same model.With the technique,higher-speed data can be decided by using lower speed device.展开更多
A high speed column-parallel CDS/ADC circuit with nonlinearity compensation is proposed in this paper.The correlated double sampling (CDS) and analog-to-digital converter (ADC) functions are integrated in a threephase...A high speed column-parallel CDS/ADC circuit with nonlinearity compensation is proposed in this paper.The correlated double sampling (CDS) and analog-to-digital converter (ADC) functions are integrated in a threephase column-parallel circuit based on two floating gate inverters and switched-capacitor network.The conversion rate of traditional single-slope ADC is speeded up by dividing quantization to coarse step and fine step.A storage capacitor is used to store the result of coarse step and locate the section of ramp signal of fine step,which can reduce the clock step from 2 n to 2 (n/2+1).The floating gate inverters are implemented to reduce the power consumption.Its induced nonlinear offset is cancelled by introducing a compensation module to the input of inverter,which can equalize the coupling path in three phases of the proposed circuit.This circuit is designed and simulated for CMOS image sensor with 640×480 pixel array using Chartered 0.18μm process.Simulation results indicate that the resolution can reach 10-bit and the maximum frame rate can reach 200 frames/s with a main clock of 10MHz.The power consumption of this circuit is less than 36.5μW with a 3.3V power supply.The proposed CDS/ADC circuit is suitable for high resolution and high speed image sensors.展开更多
文摘An efficient parallel global router using random optimization that is independent of net ordering is proposed.Parallel approaches are described and strategies guaranteeing the routing quality are discussed.The wire length model is implemented on multiprocessor,which enables the algorithm to approach feasibility of large scale problems.Timing driven model on multiprocessor and wire length model on distributed processors are also presented.The parallel algorithm greatly reduces the run time of routing.The experimental results show good speedups with no degradation of the routing quality.
文摘To keep even current distribution among DC/DC converters in a paralleled power system,an automatic master-slave control （AMSC） current sharing scheme is presented,which was implemented by a current share control IC. A current feedback loop for output voltage adjustment is proposed for low signal distortion. Moreover,a special startup control logic is designed to improve startup timing and to speed up the initial current sharing. It was completed in 1.5μm bipolar-CMOS-DMOS （BCD） technology with an area of 3.6mm^2 . Using it,a paralleled power system of two DC/DC converters capable of outputting 12V/3A was built. Experimental results show that the current sharing error at full load is kept within 1%.
文摘A novel numerical algorithm of fault location estimation for four-line fault without ground connection involving phases from each of the parallel lines is presented in this paper. It is based on one-terminal voltage and current data. The loop and nodal equations comparing faulted phase to non-faulted phase of two-parallel lines are introduced in the fault location estimation model, in which the source impedance of a remote end is not involved. The effects of load flow and fault resistance on the accuracy of fault location are effectively eliminated, therefore a precise algorithm of locating fault is derived. The algorithm is demonstrated by digital computer simulations.
文摘In this paper,the cause of bit-error is analyzed when data are decided in the optical receiver.A monolithic D-ff decision circuit is designed.It can work effectively at 622 Mb/s.Moreover,a decision method of parallel processing to improve the decision speed is presented,through which the parallel circuit can work up to 1 Gb/s using the same model.With the technique,higher-speed data can be decided by using lower speed device.
基金Supported by National Natural Science Foundation of China (No.60806010,No.60976030)
文摘A high speed column-parallel CDS/ADC circuit with nonlinearity compensation is proposed in this paper.The correlated double sampling (CDS) and analog-to-digital converter (ADC) functions are integrated in a threephase column-parallel circuit based on two floating gate inverters and switched-capacitor network.The conversion rate of traditional single-slope ADC is speeded up by dividing quantization to coarse step and fine step.A storage capacitor is used to store the result of coarse step and locate the section of ramp signal of fine step,which can reduce the clock step from 2 n to 2 (n/2+1).The floating gate inverters are implemented to reduce the power consumption.Its induced nonlinear offset is cancelled by introducing a compensation module to the input of inverter,which can equalize the coupling path in three phases of the proposed circuit.This circuit is designed and simulated for CMOS image sensor with 640×480 pixel array using Chartered 0.18μm process.Simulation results indicate that the resolution can reach 10-bit and the maximum frame rate can reach 200 frames/s with a main clock of 10MHz.The power consumption of this circuit is less than 36.5μW with a 3.3V power supply.The proposed CDS/ADC circuit is suitable for high resolution and high speed image sensors.
