Strained-Si pMOSFETs on very thin relaxed virtua l SiGe substrates are presented.The 240nm relaxed virtual Si 0.8 Ge 0.2 layer on 100nm low-temperature Si(LT-Si) is grown on Si(100) substrates by molecular be...Strained-Si pMOSFETs on very thin relaxed virtua l SiGe substrates are presented.The 240nm relaxed virtual Si 0.8 Ge 0.2 layer on 100nm low-temperature Si(LT-Si) is grown on Si(100) substrates by molecular beam epitaxy.LT-Si buffer layer is used to release stress of the SiGe layer so as to make it relaxed.DCXRD,AFM,and TEM measurements indicate that the strain relaxed degree of SiGe layer is 85%,RMS roughness is 1.02nm,and threading dislocation density is at most 107cm -2 .At room temperature,a maximum hole mobility of strained-Si pMOSFET is 140cm2/(V·s).Device performance is comparable to that of devices achieved on several microns thick relaxed virtual SiGe substrates.展开更多
Based on an analysis of symmetry, the dispersion relations near the Ai valley in strained Si1-x Gex （0≤x〈0.45）/ （001）, （111）, （101）Si are derived using the KP method with perturbation theory. These relations...Based on an analysis of symmetry, the dispersion relations near the Ai valley in strained Si1-x Gex （0≤x〈0.45）/ （001）, （111）, （101）Si are derived using the KP method with perturbation theory. These relations demonstrate that △^i levels in strained Si1-x Gex are different from the △1 level in relaxed Si1-x Gex, while the longitudinal and transverse masses （m1^＊ and mt^＊ ） are unchanged under strain. The energy shift between the △^i levels and the △1 level follows the linear deformation potential theory. Finally,a description of the conduction band （CB） edge in biaxially strained layers is given.展开更多
The process parameters are adjusted and the process procedure is simplified on the basis of precursor's work and the strained Si channel SiGe n MOSFET is fabricated successfully.This n MOSFET takes the strained...The process parameters are adjusted and the process procedure is simplified on the basis of precursor's work and the strained Si channel SiGe n MOSFET is fabricated successfully.This n MOSFET takes the strained Si layer(which is deposited on the relaxed SiGe buffer layer) as current channel and can provide a 48 5% improvement in electron mobility while keeping the gate voltage as 1V.展开更多
文摘Strained-Si pMOSFETs on very thin relaxed virtua l SiGe substrates are presented.The 240nm relaxed virtual Si 0.8 Ge 0.2 layer on 100nm low-temperature Si(LT-Si) is grown on Si(100) substrates by molecular beam epitaxy.LT-Si buffer layer is used to release stress of the SiGe layer so as to make it relaxed.DCXRD,AFM,and TEM measurements indicate that the strain relaxed degree of SiGe layer is 85%,RMS roughness is 1.02nm,and threading dislocation density is at most 107cm -2 .At room temperature,a maximum hole mobility of strained-Si pMOSFET is 140cm2/(V·s).Device performance is comparable to that of devices achieved on several microns thick relaxed virtual SiGe substrates.
文摘Based on an analysis of symmetry, the dispersion relations near the Ai valley in strained Si1-x Gex （0≤x〈0.45）/ （001）, （111）, （101）Si are derived using the KP method with perturbation theory. These relations demonstrate that △^i levels in strained Si1-x Gex are different from the △1 level in relaxed Si1-x Gex, while the longitudinal and transverse masses （m1^＊ and mt^＊ ） are unchanged under strain. The energy shift between the △^i levels and the △1 level follows the linear deformation potential theory. Finally,a description of the conduction band （CB） edge in biaxially strained layers is given.
文摘The process parameters are adjusted and the process procedure is simplified on the basis of precursor's work and the strained Si channel SiGe n MOSFET is fabricated successfully.This n MOSFET takes the strained Si layer(which is deposited on the relaxed SiGe buffer layer) as current channel and can provide a 48 5% improvement in electron mobility while keeping the gate voltage as 1V.
