容迟容断网络中基于拓扑的双时隙路由算法

在公交车载网络等类型的容迟容断网络中,可以依靠全部或者部分网络拓扑信息进行路由计算.提出一种基于拓扑信息的双时隙路由算法.该算法将网络周期离散为时隙,计算路由时,采用当前时隙和下一时隙(即双时隙)内均有效的路径作为候选路径,从而保证多数业务在链路失效前完成转发.以传输延时和延时抖动率为依据,从当前和下一时隙内均有效的路径中优选路径,以容忍可预测的链路中断;通过提供备用路径,以容忍不可预测的链路中断,保证传输的可靠性和稳定性.对上述算法进行了仿真实现和性能分析,结果表明,该算法能容忍链路中断,报文递交率较高,平均传输延时较低.

The Jitter Performance Comparison Between DLL and PLL-Based RF CMOS Oscillators

By jitter performance comparison between PLL (Phase Locked Loop) and DLL (Delay Locked Loop),a helpful equation is derived for the structure choice between DLL and PLL based synthesizers fabricated in CMOS processes to get an optimum jitter performance and power consumption.For a frequency synthesizer,a large multiple factor prefers PLL based configuration which consumes less power,while a small one needs DLL based topology which produces a better jitter performance.