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数字控制DC/DC变换器中ADC的设计 被引量:1
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作者 唐小东 王曾 +1 位作者 甄少伟 罗萍 《电子元器件应用》 2011年第7期14-16,共3页
文中介绍了一种无需外部时钟、可抵消部分工艺偏差的差分延迟线ADC,并对其建模。该ADC结构简单、控制信号在内部产生、转换速率快、功耗低,可应用在高频数字DC/DC控制芯片中。在0.13μm CMOS工艺下仿真表明,在采样电压0.7~1.5V范围内,... 文中介绍了一种无需外部时钟、可抵消部分工艺偏差的差分延迟线ADC,并对其建模。该ADC结构简单、控制信号在内部产生、转换速率快、功耗低,可应用在高频数字DC/DC控制芯片中。在0.13μm CMOS工艺下仿真表明,在采样电压0.7~1.5V范围内,该ADC输出没有明显偏移,线性度良好。 展开更多
关键词 DC/DC 延迟线adc DPWM
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A Novel ADC Architecture for Digital Voltage Regulator Module Controllers
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作者 郭健民 张科 +1 位作者 孔明 李文宏 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2006年第12期2112-2117,共6页
The design and implementation of a novel ADC architecture called ring-ADC for digital voltage regulator module controllers are presented. Based on the principle of voltage-controlled oscillators' transform from volta... The design and implementation of a novel ADC architecture called ring-ADC for digital voltage regulator module controllers are presented. Based on the principle of voltage-controlled oscillators' transform from voltage to frequency,the A/D conversion of ring-ADC achieves good linearity and precise calibration against process variations compared with the delay-line ADC. A differential pulse counting discriminator also helps decrease the power consumption of the ring-ADC. It is fabricated with a Chartered 0.35μm CMOS process, and the measurement results of the integral and differential nonlinearity performance are 0.92LSB and 1.2LSB respectively. The maximum gain error measured in ten sample chips is ± 3.85%. With sampling rate of 500kHz and when the voltage regulator module (VRM) works in steady state, the ring-ADC's average power consumption is 2.56mW. The ring-ADC is verified to meet the requirements for digital VRM controller application. 展开更多
关键词 voltage regulator modules DC-DC ring-adc delay-line adc differential pulse counting discrim-inator
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