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A Low Power/Area Digital FIR Filter Design Based on PRF Framework
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作者 王栋 Wang +2 位作者 Wei Xu Xiaoming 《High Technology Letters》 EI CAS 2002年第3期57-61,共5页
A novel DSP to ASIC (Application Specific Integrated Circuit) architecture design methodology is presented in this paper for reducing power/area consumption. Traditional methods always focus on optimizing hardware str... A novel DSP to ASIC (Application Specific Integrated Circuit) architecture design methodology is presented in this paper for reducing power/area consumption. Traditional methods always focus on optimizing hardware structure or algorithm separately. The authors propose a new method called PRF (Paralleling Reducing Folding) framework to combine hardware optimization with algorithm simplification. In the first step, paralleling, unfolding technology is applied to divide one data path into several channels and expose the redundancy of the algorithm. In the second step, reducing, decoupling theory is used to reduce computational complexity. In the last step, folding, time multiplexing method is used to merge similar components. As an exoteric methodology framework, many optimization methods can be integrated into the PRF framework. To optimize a 3N taps FIR (Fincte Impact Response) and obtain a content result, PRF methodology framework is applied. 展开更多
关键词 滤波器 数字FIR滤波器设计 建筑式设计法
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