异步Viterbi解码器同步接口的设计

提出了一种利用异步 FIFO ( First In First Out)连接异步逻辑电路与同步逻辑电路的方法 ,并设计实现了相应的异步 FIFO电路 ,作为连接异步 viterbi解码器和其他同步逻辑电路的同步接口。对异步 FIFO的级数与异步 viterbi解码器内部的时序关系进行了分析。用逻辑仿真的动态时序分析表明 ,当同步电路时钟的周期大于 130 ns时 ,具有同步接口的异步 viterbi解码器可以与同步电路正常协同工作。具有简单接口电路的异步解码器 ,既能发挥异步电路功率效率高的优点 。

数字量输入模块的设计

数字量输入模块是某通用测试台的一部分;其主要功能是接收遥测PCM码流,并对其进行解码,为后续的传输存储做准备;该设计涉及同步时钟和异步时钟的PCM解码的实现,并对解码过程中的误差问题进行了分析和说明;模块采用FPGA作为中心逻辑控制器,可以对几种电平形式的遥测PCM码进行解码,具有较强的通用性;该设计已经应经成功的应用于某通用测试台。

An Asynchronous Implementation of Add-Compare-Select Processor for Communication Systems

A novel asynchronous ACS(add-compare-select) processor for Viterbi decoder is described.It is controlled by local handshake signals instead of the globe clock.The circuits of asynchronous adder unit,asynchronous comparator unit,and asynchronous selector unit are proposed.A full-custom design of asynchronous 4-bit ACS processor is fabricated in CSMC-HJ 0.6μm CMOS 2P2M mixed-mode process.At a supply voltage of 5V,when it operates at 20MHz,the power consumption is 75.5mW.The processor has no dynamic power consumption when it awaits an opportunity in sleep mode.The results of performance test of asynchronous 4-bit ACS processor show that the average case response time 19.18ns is only 82% of the worst-case response time 23.37ns.Compared with the synchronous 4-bit ACS processor in power consumption and performance by simulation,it reveals that the asynchronous ACS processor has some advantages than the synchronous one.