Previously,a single data-path stack was adequate for data-path chips,and the complexity and size of the data-path was comparatively small.As current data-path chips,such as system-on-a-chip (SOC),become more complex,m...Previously,a single data-path stack was adequate for data-path chips,and the complexity and size of the data-path was comparatively small.As current data-path chips,such as system-on-a-chip (SOC),become more complex,multiple data-path stacks are required to implement the entire data-path.As more data-path stacks are integrated into SOC,data-path is becoming a critical part of the whole giga-scale integrated circuits (GSI) design.The traditional physical design methodology can not satisfy the data-path performance requirements,because it can not accommodate the data-path bit-sliced structure and the strict performance (such as timing,coupling,and crosstalk) constraints.Challenges in the data-path physical design are addressed.The fundamental problems and key technologies in data-path physical design are analysed.The corresponding researches and solutions in this research field are also discussed.展开更多
A wet etching process for backside via holes suitable for use on InP MMICs technologies is developed for indium phosphide substrate.PMMA is used to mount InP wafer onto glass carrier.Spattered Ta film is utilized as e...A wet etching process for backside via holes suitable for use on InP MMICs technologies is developed for indium phosphide substrate.PMMA is used to mount InP wafer onto glass carrier.Spattered Ta film is utilized as etch mask.HCl+H 3PO 4 solution realised a etch until a depth of 100μm.It is demonstrated that the wet etching backside process is controllable with large latitudes.展开更多
文摘Previously,a single data-path stack was adequate for data-path chips,and the complexity and size of the data-path was comparatively small.As current data-path chips,such as system-on-a-chip (SOC),become more complex,multiple data-path stacks are required to implement the entire data-path.As more data-path stacks are integrated into SOC,data-path is becoming a critical part of the whole giga-scale integrated circuits (GSI) design.The traditional physical design methodology can not satisfy the data-path performance requirements,because it can not accommodate the data-path bit-sliced structure and the strict performance (such as timing,coupling,and crosstalk) constraints.Challenges in the data-path physical design are addressed.The fundamental problems and key technologies in data-path physical design are analysed.The corresponding researches and solutions in this research field are also discussed.
文摘A wet etching process for backside via holes suitable for use on InP MMICs technologies is developed for indium phosphide substrate.PMMA is used to mount InP wafer onto glass carrier.Spattered Ta film is utilized as etch mask.HCl+H 3PO 4 solution realised a etch until a depth of 100μm.It is demonstrated that the wet etching backside process is controllable with large latitudes.
