Based on the physical characteristics of SiGe material,a new three-dimensional （3D） CMOS IC structure is proposed,in which the first device layer is made of Si material for nMOS devices and the second device layer i...Based on the physical characteristics of SiGe material,a new three-dimensional （3D） CMOS IC structure is proposed,in which the first device layer is made of Si material for nMOS devices and the second device layer is made of Six Ge1- x material for pMOS. The intrinsic performance of ICs with the new structure is then limited by Si nMOS.The electrical characteristics of a Si-SiGe 3D CMOS device and inverter are all simulated and analyzed by MEDICI. The simulation results indicate that the Si-SiGe 3D CMOS ICs are faster than the Si-Si 3D CMOS ICs. The delay time of the 3D Si-SiGe CMOS inverter is 2-3ps,which is shorter than that of the 3D Si-Si CMOS inverter.展开更多
A four-stage monolithic microwave integrated circuits （MMIC） low noise amplifier （LNA） operating from 23 to 36GHz is reported using commercially available 0.15μm PHEMT technology. The LNA is self-biased. To achie...A four-stage monolithic microwave integrated circuits （MMIC） low noise amplifier （LNA） operating from 23 to 36GHz is reported using commercially available 0.15μm PHEMT technology. The LNA is self-biased. To achieve a low noise characteristic, careful optimizations of gate width are performed to reduce gate resistance. Absorption circuits and an elaborate bias structure with a resistor-capacitor network are employed to improve stability. Multiple resonance points and negative feedback technologies are used to widen the bandwidth. Measurements show a noise figure （NF） of less than 2.0dB,and the lowest NF is only 1.6dB at a frequency of 31GHz. In the whole operation band,the LNA has a gain of higher than 26dB,and an input return loss and output return loss of more than 11 and 13dB,respectively. The output power at ldB compression gain of 36GHz is about 14dBm. The chip area is 2.4mm ×1mm.展开更多
An efficient parallel global router using random optimization that is independent of net ordering is proposed.Parallel approaches are described and strategies guaranteeing the routing quality are discussed.The wire le...An efficient parallel global router using random optimization that is independent of net ordering is proposed.Parallel approaches are described and strategies guaranteeing the routing quality are discussed.The wire length model is implemented on multiprocessor,which enables the algorithm to approach feasibility of large scale problems.Timing driven model on multiprocessor and wire length model on distributed processors are also presented.The parallel algorithm greatly reduces the run time of routing.The experimental results show good speedups with no degradation of the routing quality.展开更多
With the device feature's size miniaturization in very large scale integrated circuit and ultralarge scale integrated circuit towards the sub\|micron and beyond level, the next generation of IC device requires s...With the device feature's size miniaturization in very large scale integrated circuit and ultralarge scale integrated circuit towards the sub\|micron and beyond level, the next generation of IC device requires silicon wafers with more improved electrical characteristics and reliability as well as a high perfection of the wafer surface. Compared with the polished wafer with a relatively high density of crystal originated defects (e. g. COPs), silicon epi\|wafers can meet such high requirements. The current development of researches on the 150mm silicon epi\|wafers for advanced IC applications is described. The P/P\++ CMOS silicon epi\|wafers were fabricated on a PE2061 Epitaxial Reactor (made by Italian LPE Company). The material parameters of epi\|wafers, such as epi\|defects, uniformity of thickness and resistivity, transition width, and minority carrier generation lifetime for epi\|layer were characterized in detail. It is demonstrated that the 150mm silicon epi\|wafers on PE2061 can meet the stringent requirements for the advanced IC applications.展开更多
Previously,a single data-path stack was adequate for data-path chips,and the complexity and size of the data-path was comparatively small.As current data-path chips,such as system-on-a-chip (SOC),become more complex,m...Previously,a single data-path stack was adequate for data-path chips,and the complexity and size of the data-path was comparatively small.As current data-path chips,such as system-on-a-chip (SOC),become more complex,multiple data-path stacks are required to implement the entire data-path.As more data-path stacks are integrated into SOC,data-path is becoming a critical part of the whole giga-scale integrated circuits (GSI) design.The traditional physical design methodology can not satisfy the data-path performance requirements,because it can not accommodate the data-path bit-sliced structure and the strict performance (such as timing,coupling,and crosstalk) constraints.Challenges in the data-path physical design are addressed.The fundamental problems and key technologies in data-path physical design are analysed.The corresponding researches and solutions in this research field are also discussed.展开更多
s:A divide- by- 12 8/ 12 9or6 4/ 6 5 dual- modulus prescaler based on new optimized structure and dynam ic circuit technique im plem ented in 0 .2 5 μm CMOS digital technology is described.New optimized structure re...s:A divide- by- 12 8/ 12 9or6 4/ 6 5 dual- modulus prescaler based on new optimized structure and dynam ic circuit technique im plem ented in 0 .2 5 μm CMOS digital technology is described.New optimized structure reduces the propagation delay and has higher operating speed.Based on this structure,an im proved D- flip- flop(DFF) using dynam ic circuit technique is proposed.A prototype is fabricated and the measured results show that this prescaler works well in gigahertz frequency range and consumes only35 m W(including three power- hungry output buffers) when the input frequency is2 .5 GHz and the power supply voltage is2 .5 V.Due to its excellent perform ance,the prescaler could be applied to many RF system s.展开更多
This paper presents the total dose radiation performance of 0.8μm SOI CMOS devices fabricated with full dose SIMOX technology. The radiation performance is characterized by threshold voltage shifts and leakage curren...This paper presents the total dose radiation performance of 0.8μm SOI CMOS devices fabricated with full dose SIMOX technology. The radiation performance is characterized by threshold voltage shifts and leakage currents of transistors and standby currents of ASIC as functions of the total dose up to 500krad（Si）. The experimental results show that the worst case threshold voltage shifts of front channels are less than 320mV for pMOS transistors under off-gate radiation bias at 1Mrad（Si） and less than 120mV for nMOS transistors under on-gate radiation bias. No significant radiation-induced leakage current is observed in transistors to 1Mrad （Si）. The standby currents of ASIC are less than the specification of 5μA over the total dose range of 500krad（Si）.展开更多
A novel fabrication process related to a smoothly wet chemical etching profile o f InP-based epitaxial layers in the crystal direction of [01for an InP-based monol ithic vertically integrated transmitter with an M...A novel fabrication process related to a smoothly wet chemical etching profile o f InP-based epitaxial layers in the crystal direction of [01for an InP-based monol ithic vertically integrated transmitter with an MQW laser diode and a heterojunction bipolar tran sistors driver circuit is described.A clear eye output diagram via an O/E converter is demonstrat ed und er a 1.25Gb/s non-return-zero pseudorandom code with a pattern length of 2 the integrated transmitter has a power dissipation of about 120mW with an optical output of 2dBm.展开更多
We propose a novel thermal-conscious power model for integrated circuits that can accurately predict power and temperature under voltage scaling. Experimental results show that the leakage power consumption is underes...We propose a novel thermal-conscious power model for integrated circuits that can accurately predict power and temperature under voltage scaling. Experimental results show that the leakage power consumption is underestimated by 52 % if thermal effects are omitted. Furthermore, an inconsistency arises when energy and temperature are simultaneously optimized by dynamic voltage scaling. Temperature is a limiting factor for future integrated circuits,and the thermal optimization approach can attain a temperature reduction of up to 12℃ with less than 1.8% energy penalty compared with the energy optimization one.展开更多
An equivalent circuit for a novel RF integrated inductor with ferrite thin-film is derived. The enhancement of the magnetic ferrite thin-film on the inductance （L） and quality factor （Q） of the inductor is analyze...An equivalent circuit for a novel RF integrated inductor with ferrite thin-film is derived. The enhancement of the magnetic ferrite thin-film on the inductance （L） and quality factor （Q） of the inductor is analyzed. Circuit element parameters are extracted from RF measurements. Compared with the reference air-core inductor without magnetic film, L and Q of the ferrite thin-film inductor are 17% and 40% higher at 2GHz,respectively. Both the equivalent circuit analysis and test results demonstrate significant enhancement of the performance of RF integration inductors by ferrite thin-film integration.展开更多
A 4-12GHz wideband power amplifier,using a balanced configuration with a strip line Lange coupler, is designed and fabricated. This power amplifier shows a maximum continuous wave output power of 29.5dBm at 8GHz cente...A 4-12GHz wideband power amplifier,using a balanced configuration with a strip line Lange coupler, is designed and fabricated. This power amplifier shows a maximum continuous wave output power of 29.5dBm at 8GHz center frequency with an associated gain of 8.5dB and a gain flatness of ＋ /- 0.6dB in the 4-12GHz frequency range.展开更多
A CMOS fully-differential 2.4GHz ∑-△ frequency synthesizer for Gaussian minimum shift keying （GMSK）modulation is presented. A pre-compensation fractional-N phase-locked loop（PLL）is adopted in the modulator.The t...A CMOS fully-differential 2.4GHz ∑-△ frequency synthesizer for Gaussian minimum shift keying （GMSK）modulation is presented. A pre-compensation fractional-N phase-locked loop（PLL）is adopted in the modulator.The transfer function of the type- Ⅱ third-order phase-locked loop is deduced,and the important parameters that affect the loop transfer function are pointed out. Methods to calibrate the important loop parameters arc introduced. A differential tuned LC-VCO and a fully-differential charge pump are adopted in the PLL design. The designed circuits are simulated in a 0.18gm 1P6M CMOS process. The power consumption of the PLL is only about llmW with the low power consideration in building blocks design, and the data rate of the modulator can reach 2Mb/s.展开更多
A power amplifier MIC with power combining based on AlGaN/GaN HEMTs was fabricated and measured. The amplifier consists of four 10 × 120μm transistors. A Wilkinson splitters and combining were used to divide and...A power amplifier MIC with power combining based on AlGaN/GaN HEMTs was fabricated and measured. The amplifier consists of four 10 × 120μm transistors. A Wilkinson splitters and combining were used to divide and combine the power. By biasing the amplifier at VDS = 40V, IDS = 0.9A, a maximum CW output power of 41.4dBm with a maximum power added efficiency （PAE） of 32.54% and a power combine efficiency of 69% was achieved at 5.4GHz.展开更多
文摘Based on the physical characteristics of SiGe material,a new three-dimensional （3D） CMOS IC structure is proposed,in which the first device layer is made of Si material for nMOS devices and the second device layer is made of Six Ge1- x material for pMOS. The intrinsic performance of ICs with the new structure is then limited by Si nMOS.The electrical characteristics of a Si-SiGe 3D CMOS device and inverter are all simulated and analyzed by MEDICI. The simulation results indicate that the Si-SiGe 3D CMOS ICs are faster than the Si-Si 3D CMOS ICs. The delay time of the 3D Si-SiGe CMOS inverter is 2-3ps,which is shorter than that of the 3D Si-Si CMOS inverter.
文摘A four-stage monolithic microwave integrated circuits （MMIC） low noise amplifier （LNA） operating from 23 to 36GHz is reported using commercially available 0.15μm PHEMT technology. The LNA is self-biased. To achieve a low noise characteristic, careful optimizations of gate width are performed to reduce gate resistance. Absorption circuits and an elaborate bias structure with a resistor-capacitor network are employed to improve stability. Multiple resonance points and negative feedback technologies are used to widen the bandwidth. Measurements show a noise figure （NF） of less than 2.0dB,and the lowest NF is only 1.6dB at a frequency of 31GHz. In the whole operation band,the LNA has a gain of higher than 26dB,and an input return loss and output return loss of more than 11 and 13dB,respectively. The output power at ldB compression gain of 36GHz is about 14dBm. The chip area is 2.4mm ×1mm.
文摘An efficient parallel global router using random optimization that is independent of net ordering is proposed.Parallel approaches are described and strategies guaranteeing the routing quality are discussed.The wire length model is implemented on multiprocessor,which enables the algorithm to approach feasibility of large scale problems.Timing driven model on multiprocessor and wire length model on distributed processors are also presented.The parallel algorithm greatly reduces the run time of routing.The experimental results show good speedups with no degradation of the routing quality.
基金Project Supported by National Ninth5-year Plan of China.
文摘With the device feature's size miniaturization in very large scale integrated circuit and ultralarge scale integrated circuit towards the sub\|micron and beyond level, the next generation of IC device requires silicon wafers with more improved electrical characteristics and reliability as well as a high perfection of the wafer surface. Compared with the polished wafer with a relatively high density of crystal originated defects (e. g. COPs), silicon epi\|wafers can meet such high requirements. The current development of researches on the 150mm silicon epi\|wafers for advanced IC applications is described. The P/P\++ CMOS silicon epi\|wafers were fabricated on a PE2061 Epitaxial Reactor (made by Italian LPE Company). The material parameters of epi\|wafers, such as epi\|defects, uniformity of thickness and resistivity, transition width, and minority carrier generation lifetime for epi\|layer were characterized in detail. It is demonstrated that the 150mm silicon epi\|wafers on PE2061 can meet the stringent requirements for the advanced IC applications.
文摘Previously,a single data-path stack was adequate for data-path chips,and the complexity and size of the data-path was comparatively small.As current data-path chips,such as system-on-a-chip (SOC),become more complex,multiple data-path stacks are required to implement the entire data-path.As more data-path stacks are integrated into SOC,data-path is becoming a critical part of the whole giga-scale integrated circuits (GSI) design.The traditional physical design methodology can not satisfy the data-path performance requirements,because it can not accommodate the data-path bit-sliced structure and the strict performance (such as timing,coupling,and crosstalk) constraints.Challenges in the data-path physical design are addressed.The fundamental problems and key technologies in data-path physical design are analysed.The corresponding researches and solutions in this research field are also discussed.
文摘s:A divide- by- 12 8/ 12 9or6 4/ 6 5 dual- modulus prescaler based on new optimized structure and dynam ic circuit technique im plem ented in 0 .2 5 μm CMOS digital technology is described.New optimized structure reduces the propagation delay and has higher operating speed.Based on this structure,an im proved D- flip- flop(DFF) using dynam ic circuit technique is proposed.A prototype is fabricated and the measured results show that this prescaler works well in gigahertz frequency range and consumes only35 m W(including three power- hungry output buffers) when the input frequency is2 .5 GHz and the power supply voltage is2 .5 V.Due to its excellent perform ance,the prescaler could be applied to many RF system s.
文摘This paper presents the total dose radiation performance of 0.8μm SOI CMOS devices fabricated with full dose SIMOX technology. The radiation performance is characterized by threshold voltage shifts and leakage currents of transistors and standby currents of ASIC as functions of the total dose up to 500krad（Si）. The experimental results show that the worst case threshold voltage shifts of front channels are less than 320mV for pMOS transistors under off-gate radiation bias at 1Mrad（Si） and less than 120mV for nMOS transistors under on-gate radiation bias. No significant radiation-induced leakage current is observed in transistors to 1Mrad （Si）. The standby currents of ASIC are less than the specification of 5μA over the total dose range of 500krad（Si）.
文摘A novel fabrication process related to a smoothly wet chemical etching profile o f InP-based epitaxial layers in the crystal direction of [01for an InP-based monol ithic vertically integrated transmitter with an MQW laser diode and a heterojunction bipolar tran sistors driver circuit is described.A clear eye output diagram via an O/E converter is demonstrat ed und er a 1.25Gb/s non-return-zero pseudorandom code with a pattern length of 2 the integrated transmitter has a power dissipation of about 120mW with an optical output of 2dBm.
文摘We propose a novel thermal-conscious power model for integrated circuits that can accurately predict power and temperature under voltage scaling. Experimental results show that the leakage power consumption is underestimated by 52 % if thermal effects are omitted. Furthermore, an inconsistency arises when energy and temperature are simultaneously optimized by dynamic voltage scaling. Temperature is a limiting factor for future integrated circuits,and the thermal optimization approach can attain a temperature reduction of up to 12℃ with less than 1.8% energy penalty compared with the energy optimization one.
文摘An equivalent circuit for a novel RF integrated inductor with ferrite thin-film is derived. The enhancement of the magnetic ferrite thin-film on the inductance （L） and quality factor （Q） of the inductor is analyzed. Circuit element parameters are extracted from RF measurements. Compared with the reference air-core inductor without magnetic film, L and Q of the ferrite thin-film inductor are 17% and 40% higher at 2GHz,respectively. Both the equivalent circuit analysis and test results demonstrate significant enhancement of the performance of RF integration inductors by ferrite thin-film integration.
文摘A 4-12GHz wideband power amplifier,using a balanced configuration with a strip line Lange coupler, is designed and fabricated. This power amplifier shows a maximum continuous wave output power of 29.5dBm at 8GHz center frequency with an associated gain of 8.5dB and a gain flatness of ＋ /- 0.6dB in the 4-12GHz frequency range.
文摘A CMOS fully-differential 2.4GHz ∑-△ frequency synthesizer for Gaussian minimum shift keying （GMSK）modulation is presented. A pre-compensation fractional-N phase-locked loop（PLL）is adopted in the modulator.The transfer function of the type- Ⅱ third-order phase-locked loop is deduced,and the important parameters that affect the loop transfer function are pointed out. Methods to calibrate the important loop parameters arc introduced. A differential tuned LC-VCO and a fully-differential charge pump are adopted in the PLL design. The designed circuits are simulated in a 0.18gm 1P6M CMOS process. The power consumption of the PLL is only about llmW with the low power consideration in building blocks design, and the data rate of the modulator can reach 2Mb/s.
文摘A power amplifier MIC with power combining based on AlGaN/GaN HEMTs was fabricated and measured. The amplifier consists of four 10 × 120μm transistors. A Wilkinson splitters and combining were used to divide and combine the power. By biasing the amplifier at VDS = 40V, IDS = 0.9A, a maximum CW output power of 41.4dBm with a maximum power added efficiency （PAE） of 32.54% and a power combine efficiency of 69% was achieved at 5.4GHz.
