It is a widely discussed question that where the web latency comes from. In this paper, we propose a novel chunk-level latency dependence model to give a better illustration of the web latency. Based on the fact that ...It is a widely discussed question that where the web latency comes from. In this paper, we propose a novel chunk-level latency dependence model to give a better illustration of the web latency. Based on the fact that web content is delivered in chunk sequence, and clients care more about whole page retrieval latency, this paper carries out a detailed study on how the chunk sequence and relations affect the web retrieval latency. A series of thorough experiments are also conducted and data analysis are also made. The result is useful for further study on how to reduce the web latency.展开更多
Discussed is a review and perspective of architecture, materials and process technology for dynamic random access memory(DRAM) applications. Key challenges of the transistor and capacitor scaling from DRAM will be rev...Discussed is a review and perspective of architecture, materials and process technology for dynamic random access memory(DRAM) applications. Key challenges of the transistor and capacitor scaling from DRAM will be reviewed. To continue scaling down, multi-gate devices with very thin silicon channels are most promising. Several architectures like Fin-field effect transistor(Fin-FET), Wafer bonded double gate and silicon on nothing(SON) gate-all-around have been demonstrated with good electrical characteristics. An overview of the evolution of capacitor technology is also presented from the early days of planar poly/insulator/silicon(PIS) capacitors to the metal/insulator/metal(MIM) capacitors used for today 50nm technology node and below. In comparing Ta2O5, HfO2 and Al2O3 as high-k dielectric for use in DRAM technology, Al2O3 is found to give a good compromise between capacitor performance and manufacturability used in MIM architecture.展开更多
Leakage power is the dominant source of power dissipation for Sub-100 nm VLSI （very large scale integration） circuits. Various techniques were proposed to reduce the leakage power at nano-scale; one of these techniq...Leakage power is the dominant source of power dissipation for Sub-100 nm VLSI （very large scale integration） circuits. Various techniques were proposed to reduce the leakage power at nano-scale; one of these techniques is MTV （multi-threshold voltage） In this paper, the exact and optimal value of threshold voltage （Vth） for each transistor in any sequential circuit in the design is found, so that the value of the total leakage current in the design is at the minimum. This could be achieved by applying AI （artificial intelligence） search algorithm. The proposed algorithm is called LOAIS （leakage optimization using AI search）. LOAIS exploits the total slack time of each transistor＇s location and their contributions in the leakage current. It is introduced by AI heuristic search algorithms under 22 nm BSIM4 predictive technology model. The proposed approach saves around 80% of the sub-threshold leakage current without degrading the performance of the circuit.展开更多
文摘It is a widely discussed question that where the web latency comes from. In this paper, we propose a novel chunk-level latency dependence model to give a better illustration of the web latency. Based on the fact that web content is delivered in chunk sequence, and clients care more about whole page retrieval latency, this paper carries out a detailed study on how the chunk sequence and relations affect the web retrieval latency. A series of thorough experiments are also conducted and data analysis are also made. The result is useful for further study on how to reduce the web latency.
文摘Discussed is a review and perspective of architecture, materials and process technology for dynamic random access memory(DRAM) applications. Key challenges of the transistor and capacitor scaling from DRAM will be reviewed. To continue scaling down, multi-gate devices with very thin silicon channels are most promising. Several architectures like Fin-field effect transistor(Fin-FET), Wafer bonded double gate and silicon on nothing(SON) gate-all-around have been demonstrated with good electrical characteristics. An overview of the evolution of capacitor technology is also presented from the early days of planar poly/insulator/silicon(PIS) capacitors to the metal/insulator/metal(MIM) capacitors used for today 50nm technology node and below. In comparing Ta2O5, HfO2 and Al2O3 as high-k dielectric for use in DRAM technology, Al2O3 is found to give a good compromise between capacitor performance and manufacturability used in MIM architecture.
文摘Leakage power is the dominant source of power dissipation for Sub-100 nm VLSI （very large scale integration） circuits. Various techniques were proposed to reduce the leakage power at nano-scale; one of these techniques is MTV （multi-threshold voltage） In this paper, the exact and optimal value of threshold voltage （Vth） for each transistor in any sequential circuit in the design is found, so that the value of the total leakage current in the design is at the minimum. This could be achieved by applying AI （artificial intelligence） search algorithm. The proposed algorithm is called LOAIS （leakage optimization using AI search）. LOAIS exploits the total slack time of each transistor＇s location and their contributions in the leakage current. It is introduced by AI heuristic search algorithms under 22 nm BSIM4 predictive technology model. The proposed approach saves around 80% of the sub-threshold leakage current without degrading the performance of the circuit.
