A new configuration for delay cells used in voltage controlled oscillators is presented. A jitter comparison between the source-coupled differential delay cell and the proposed CMOS inverter based delay cell is given....A new configuration for delay cells used in voltage controlled oscillators is presented. A jitter comparison between the source-coupled differential delay cell and the proposed CMOS inverter based delay cell is given. A new method to optimize loop parameters based on low-jitter in PLL is also introduced. A low-jitter 1.25GHz Serdes is implemented in a 0.35μm standard 2P3M CMOS process. The result shows that the RJ （random jitter） RMS of 1.25GHz data rate series output is 2. 3ps （0. 0015UI） and RJ （1 sigma） is 0. 0035UI. A phase noise measurement shows - 120dBc/Hz@100kHz at 1111100000 clock-pattern data out.展开更多
A behavior model for the receiver of the Ethernet passive optical network（EPON） is presented. The model consists of a fiber, a photodetector, a transimpedance amplifier （TIA） followed by a limiting amplifier and a...A behavior model for the receiver of the Ethernet passive optical network（EPON） is presented. The model consists of a fiber, a photodetector, a transimpedance amplifier （TIA） followed by a limiting amplifier and a clock and data recovery＇ circuit （CDR）. Each sub-model is constructed based on the architecture of a circuit. The noise and jitter in each block such as shot noise, thermal noise, deterministic and random jitter are also considered. The performance of the whole receiver can be evaluated by the simulation of the behavior model, which is faster than the ordinary circuit model and more accurate than the analytical model. The whole model is implemented with C ＋＋ and simulated in Microsoft Visual C ＋＋ 6. 0. Using the Monte Carlo method, the EPON receiver is simulated. The simulation results show a good agreement with experimental ones.展开更多
文摘A new configuration for delay cells used in voltage controlled oscillators is presented. A jitter comparison between the source-coupled differential delay cell and the proposed CMOS inverter based delay cell is given. A new method to optimize loop parameters based on low-jitter in PLL is also introduced. A low-jitter 1.25GHz Serdes is implemented in a 0.35μm standard 2P3M CMOS process. The result shows that the RJ （random jitter） RMS of 1.25GHz data rate series output is 2. 3ps （0. 0015UI） and RJ （1 sigma） is 0. 0035UI. A phase noise measurement shows - 120dBc/Hz@100kHz at 1111100000 clock-pattern data out.
文摘A behavior model for the receiver of the Ethernet passive optical network（EPON） is presented. The model consists of a fiber, a photodetector, a transimpedance amplifier （TIA） followed by a limiting amplifier and a clock and data recovery＇ circuit （CDR）. Each sub-model is constructed based on the architecture of a circuit. The noise and jitter in each block such as shot noise, thermal noise, deterministic and random jitter are also considered. The performance of the whole receiver can be evaluated by the simulation of the behavior model, which is faster than the ordinary circuit model and more accurate than the analytical model. The whole model is implemented with C ＋＋ and simulated in Microsoft Visual C ＋＋ 6. 0. Using the Monte Carlo method, the EPON receiver is simulated. The simulation results show a good agreement with experimental ones.
