指令压缩技术能够克服传统超长指令字(very long instruction word,VLIW)结构的指令高速缓冲(cache)中长指令字密度低的缺陷,使长指令字中的各条指令能紧密地排列在高速缓冲行(cache line)中,但可能导致长指令字分置于两个cache line,...指令压缩技术能够克服传统超长指令字(very long instruction word,VLIW)结构的指令高速缓冲(cache)中长指令字密度低的缺陷,使长指令字中的各条指令能紧密地排列在高速缓冲行(cache line)中,但可能导致长指令字分置于两个cache line,使其不能同时参与取指与发射,从而成为处理器的性能瓶颈.受到分置cache line的影响,传统提升循环效率的软件流水方法性能下降.高性能变长指令发射窗的机制能够解决分离指令字带来的取指发射问题,为取指流水线提供高效连续的指令流,特别地,该机制缓存循环的一次迭代,硬件支持循环的软件流水,有效地增强VLIW结构的数字信号处理器(digital signal processor,DSP)的性能.通过搭建时钟精确的处理器仿真模型,并基于DSP?IMG库上进行仿真,结果显示,采用两级指令发射窗机制,平均性能提高约21.89%.展开更多
5G baseband signal processing places greater real-time and reliability requirements on hardware.Based on the architecture of the MaPU,a reconfigurable computing architecture is proposed according to the characteristic...5G baseband signal processing places greater real-time and reliability requirements on hardware.Based on the architecture of the MaPU,a reconfigurable computing architecture is proposed according to the characteristics of the 5G baseband signal processing.A dedicated instruction set for 5G baseband signal processing is proposed.The corresponding functional units are designed for reuse of hardware resources.A redirected register file is proposed to address latency and power consumption issues in internetwork.A two-dimensional code compression scheme is proposed for cases in which the use ratio of instruction memory is low.The access mode of the data memory is extended,the performance is improved and the power consumption is reduced.The throughput of 5G baseband processing algorithm is one to two orders of magnitude higher than that of the TMS320C6670 with less power consumption.The silicon area evaluated by layout is 5.8 mm2,which is 1/6 of the MaPU’s.The average power consumption is 0.7 W,which is 1/5 of the MaPU’s.展开更多
文摘指令压缩技术能够克服传统超长指令字(very long instruction word,VLIW)结构的指令高速缓冲(cache)中长指令字密度低的缺陷,使长指令字中的各条指令能紧密地排列在高速缓冲行(cache line)中,但可能导致长指令字分置于两个cache line,使其不能同时参与取指与发射,从而成为处理器的性能瓶颈.受到分置cache line的影响,传统提升循环效率的软件流水方法性能下降.高性能变长指令发射窗的机制能够解决分离指令字带来的取指发射问题,为取指流水线提供高效连续的指令流,特别地,该机制缓存循环的一次迭代,硬件支持循环的软件流水,有效地增强VLIW结构的数字信号处理器(digital signal processor,DSP)的性能.通过搭建时钟精确的处理器仿真模型,并基于DSP?IMG库上进行仿真,结果显示,采用两级指令发射窗机制,平均性能提高约21.89%.
基金Project(XDA-06010402)supported by the Strategic Priority Research Program of Chinese Academy of SciencesProject(Y5S7061G51)supported by the Youth Innovation Promotion Association of Chinese Academy of Sciences
文摘5G baseband signal processing places greater real-time and reliability requirements on hardware.Based on the architecture of the MaPU,a reconfigurable computing architecture is proposed according to the characteristics of the 5G baseband signal processing.A dedicated instruction set for 5G baseband signal processing is proposed.The corresponding functional units are designed for reuse of hardware resources.A redirected register file is proposed to address latency and power consumption issues in internetwork.A two-dimensional code compression scheme is proposed for cases in which the use ratio of instruction memory is low.The access mode of the data memory is extended,the performance is improved and the power consumption is reduced.The throughput of 5G baseband processing algorithm is one to two orders of magnitude higher than that of the TMS320C6670 with less power consumption.The silicon area evaluated by layout is 5.8 mm2,which is 1/6 of the MaPU’s.The average power consumption is 0.7 W,which is 1/5 of the MaPU’s.
