任何一种话的语言(a living language)都是随着时代的发展而发展。计算机的产生与迅猛发展使一些新词应运而生。从新词的构成方式来看,很多词属于 acronym,即由某一名称的字首字母组合而成,常见的如:1.Cobol:Common Business Oriented L...任何一种话的语言(a living language)都是随着时代的发展而发展。计算机的产生与迅猛发展使一些新词应运而生。从新词的构成方式来看,很多词属于 acronym,即由某一名称的字首字母组合而成,常见的如:1.Cobol:Common Business Oriented Language(a computer languagewidely used in business and data processing)通用事物语言(在商业及数据处理中广泛使用的一种计算机语言)展开更多
5G baseband signal processing places greater real-time and reliability requirements on hardware.Based on the architecture of the MaPU,a reconfigurable computing architecture is proposed according to the characteristic...5G baseband signal processing places greater real-time and reliability requirements on hardware.Based on the architecture of the MaPU,a reconfigurable computing architecture is proposed according to the characteristics of the 5G baseband signal processing.A dedicated instruction set for 5G baseband signal processing is proposed.The corresponding functional units are designed for reuse of hardware resources.A redirected register file is proposed to address latency and power consumption issues in internetwork.A two-dimensional code compression scheme is proposed for cases in which the use ratio of instruction memory is low.The access mode of the data memory is extended,the performance is improved and the power consumption is reduced.The throughput of 5G baseband processing algorithm is one to two orders of magnitude higher than that of the TMS320C6670 with less power consumption.The silicon area evaluated by layout is 5.8 mm2,which is 1/6 of the MaPU’s.The average power consumption is 0.7 W,which is 1/5 of the MaPU’s.展开更多
This letter presents a programmable single-chip architecture for Multi-lnput and Multi-Output （M1MO） OFDM baseband receiver. The architecture comprises a Single Instruction Multiple Data （SIMD） DSP core and three ...This letter presents a programmable single-chip architecture for Multi-lnput and Multi-Output （M1MO） OFDM baseband receiver. The architecture comprises a Single Instruction Multiple Data （SIMD） DSP core and three coprocessors that are used for synchronization, FFT and channel decoder. In this MIMO OFDM system, the Zero Correlation Zone （ZCZ） code is used as the synchronization word preamble of packet in the physical layer in order to avoid the interference from other transmitting antennas. Furthermore, a simple channel estimation algorithm is proposed which is appropriate tbr the SIMD DSP computation.展开更多
To efficiently exploit the performance of single instruction multiple data （SIMD） architectures for video coding, a parallel memory architecture with power-of-two memory modules is proposed. It employs two novel ske...To efficiently exploit the performance of single instruction multiple data （SIMD） architectures for video coding, a parallel memory architecture with power-of-two memory modules is proposed. It employs two novel skewing schemes to provide conflict-free access to adjacent elements （8-bit and 16-bit data types） or with power-of-two intervals in both horizontal and vertical directions, which were not possible in previous parallel memory architectures. Area consumptions and delay estimations are given respectively with 4, 8 and 16 memory modules. Under a 0.18-pm CMOS technology, the synthesis results show that the proposed system can achieve 230 MHz clock frequency with 16 memory modules at the cost of 19k gates when read and write latencies are 3 and 2 clock cycles, respectively. We implement the proposed parallel memory architecture on a video signal processor （VSP）. The results show that VSP enhanced with the proposed architecture achieves 1.28× speedups for H.264 real-time decoding.展开更多
文摘任何一种话的语言(a living language)都是随着时代的发展而发展。计算机的产生与迅猛发展使一些新词应运而生。从新词的构成方式来看,很多词属于 acronym,即由某一名称的字首字母组合而成,常见的如:1.Cobol:Common Business Oriented Language(a computer languagewidely used in business and data processing)通用事物语言(在商业及数据处理中广泛使用的一种计算机语言)
基金Project(XDA-06010402)supported by the Strategic Priority Research Program of Chinese Academy of SciencesProject(Y5S7061G51)supported by the Youth Innovation Promotion Association of Chinese Academy of Sciences
文摘5G baseband signal processing places greater real-time and reliability requirements on hardware.Based on the architecture of the MaPU,a reconfigurable computing architecture is proposed according to the characteristics of the 5G baseband signal processing.A dedicated instruction set for 5G baseband signal processing is proposed.The corresponding functional units are designed for reuse of hardware resources.A redirected register file is proposed to address latency and power consumption issues in internetwork.A two-dimensional code compression scheme is proposed for cases in which the use ratio of instruction memory is low.The access mode of the data memory is extended,the performance is improved and the power consumption is reduced.The throughput of 5G baseband processing algorithm is one to two orders of magnitude higher than that of the TMS320C6670 with less power consumption.The silicon area evaluated by layout is 5.8 mm2,which is 1/6 of the MaPU’s.The average power consumption is 0.7 W,which is 1/5 of the MaPU’s.
基金Supported by the National Natural Science Foundation of China (No.60476013).
文摘This letter presents a programmable single-chip architecture for Multi-lnput and Multi-Output （M1MO） OFDM baseband receiver. The architecture comprises a Single Instruction Multiple Data （SIMD） DSP core and three coprocessors that are used for synchronization, FFT and channel decoder. In this MIMO OFDM system, the Zero Correlation Zone （ZCZ） code is used as the synchronization word preamble of packet in the physical layer in order to avoid the interference from other transmitting antennas. Furthermore, a simple channel estimation algorithm is proposed which is appropriate tbr the SIMD DSP computation.
基金Project (No. 2005AA1Z1271) supported by the Hi-Tech Research and Development Program (863) of China
文摘To efficiently exploit the performance of single instruction multiple data （SIMD） architectures for video coding, a parallel memory architecture with power-of-two memory modules is proposed. It employs two novel skewing schemes to provide conflict-free access to adjacent elements （8-bit and 16-bit data types） or with power-of-two intervals in both horizontal and vertical directions, which were not possible in previous parallel memory architectures. Area consumptions and delay estimations are given respectively with 4, 8 and 16 memory modules. Under a 0.18-pm CMOS technology, the synthesis results show that the proposed system can achieve 230 MHz clock frequency with 16 memory modules at the cost of 19k gates when read and write latencies are 3 and 2 clock cycles, respectively. We implement the proposed parallel memory architecture on a video signal processor （VSP）. The results show that VSP enhanced with the proposed architecture achieves 1.28× speedups for H.264 real-time decoding.
