一种低噪声C类LC压控振荡器的设计

为了改善压控振荡器相位噪声,基于40 nm CMOS工艺,设计一种低噪声C类LC压控振荡器。交叉耦合NMOS对管通过电流镜偏置作为电路的电流源,并采用共模反馈偏置电路使交叉耦合PMOS对管工作在饱和区,保证LC压控振荡器实现C类振荡。通过差分可变电容的设计,压控振荡器的增益减小,压控振荡器的相位噪声得到改善。设计了4组开关电容进行调节,增大压控振荡器的调谐范围。仿真结果表明,处于1.2 V的电压下,压控振荡器振荡频率范围在4.14~5.7 GHz,频率调谐范围变化率达到31.2%,相位噪声为-112.8 dBc/Hz。

振荡器相位噪声对双站SAR成像影响分析

研究了振荡器的相位噪声对双站SAR系统成像的影响.根据振荡器的相位噪声的幂律模型,给出了双站SAR回波相位误差模型影响及其与单站模型的差异,基于相位噪声变化快慢对成像影响的差异,将其划分成线性误差、二次相位误差和高频误差三种分量,分别定量分析了它们对双站SAR图像偏移、聚焦及副瓣特性的影响.

不同类型噪声作用下振荡器的相位噪声分析

相位噪声是振荡器最重要的性能指标.文中从描述振荡器的非线性微分方程出发,提出将噪声作为非线性微分方程的一项,通过建立随机非线性微分方程来分析振荡器的相位噪声,为振荡器的相位噪声提出了一种新的分析方法.用这种方法,在相同强度下,针对白噪声分别为加性和乘性的情形,分析其产生的相位噪声,得出了乘性噪声产生的相位噪声远大于加性噪声所产生的相位噪声的结论.

905MHz低相噪声表面波振荡器的设计

本文分析了声表面波谐振器的性能 ,论述了声表面波振荡器的工作原理及设计方法 ,最终完成中心频率为 90 5MHz的振荡电路 ,相位噪声低于 - 110dBc/Hz/ 1kHz。

8mm频段低相位噪声振荡器的设计与实现

一、前言近年来毫米波技术发展迅速,各种毫米波系统开始研究和使用,随着毫米波系统的技术指标的提高,对毫米波源的要求愈来愈高。本文试图在提高毫米波源的指标上做些探讨。二、设计低相位噪声振荡器的一些原则对于振荡器的短稳指标,通常用频域法来描述,即相位噪声指标。振荡器的相位噪声密度与载波之比由下式给出:

基于单端开路系统函数的介质振荡器的设计

介绍了X波段的介质谐振腔稳频的振荡电路的理论分析和数值仿真设计.振荡器由高介电常数的介质谐振腔形成的反馈回路和单端开路负阻振荡器构成.谐振腔的设计可以用一个简单的传输线型的模型进行仿真,使得理论分析得以试验的证实.电路的仿真结果和测试结果吻合良好,其工作在10.576GHz,输出功率在16dBm,这种振荡器可以应用在很多微波系统.

相位噪声对双基SAR成像影响仿真分析

通过仿真分析研究了振荡器相位噪声对双基SAR成像的影响。根据振荡器相位噪声的幂律模型,建立了含有相位噪声的双基SAR相位同步误差模型。利用白噪声滤波法得到幂律谱中有色噪声的时域序列,在回波仿真过程中注入相位噪声,通过双基SAR成像处理和点目标质量评估,对比分析了在不同分辨率下相位噪声对成像性能的影响以及高分辨率成像对噪声的要求。仿真发现相位噪声主要使方位向PSLR、ISLR变大并使旁瓣上升,其中积分旁瓣比和峰值旁瓣比对噪声最敏感,并且方位向分辨率越高对噪声越敏感。文中的分析方法和结论对于双基SAR的工程实现具有一定的指导意义。

CMOS毫米波低相噪级联双锁相环频率综合器设计

采用65 nm CMOS工艺,设计了一种低相噪级联双锁相环毫米波频率综合器。该频率综合器采用两级锁相环级联的结构,减轻了单级毫米波频率综合器带内和带外相位噪声受带宽的影响。时间数字转换器采用游标卡尺型结构,改善了PVT变化下时间数字转换器的量化线性度。数字环路滤波器采用自动环路增益控制技术来自适应调节环路带宽,以提高频率综合器的性能。振荡器采用噪声循环技术,减小了注入到谐振腔的噪声,进而改善了振荡器的相位噪声。后仿真结果表明,在1.2 V电源电压下,该频率综合器可输出的频率范围为22~26 GHz,在输出频率为24 GHz时,相位噪声为-104.8 dBc/Hz@1 MHz,功耗为46.8 mW。

基于收发分置SAR雷达的相位同步通信

通常振荡器相位噪声能够影响收发分置雷达的性能,从而降低了多基地合成孔径雷达的成像效果,因此,减少振荡器相位噪声对于成像来说非常重要。给出了通过使用同步通信来量化抵消振荡器相位噪声的方法,给出了不同的同步策略,对它们的性能进行了分析,并着重对来自于接收机噪声、频谱混叠、插值及滤波误匹配的同步通信误差进行了研究。

基于围线积分双谱的雷达辐射源信号个体特征提取

雷达辐射源信号因无法避免的振荡器相位噪声影响而具有无意调制个体特征现象。特定辐射源识别(SEI)技术研究立足于从截获的辐射源信号中提取细微且稳健的特征,这些特征是由特定辐射源个体所决定的指纹信息。采用围线积分双谱提取由振荡器相位噪声所造成的无意调制个体特征,并将围线积分双谱的均值、波形熵和双谱熵作为量化特征衡量不同雷达辐射源之间的个体差异。仿真实验表明,提取的量化特征在一定的信噪比环境下较好地体现辐射源之间的个体差异性,并且能够实现辐射源个体识别。

A low-phase-noise and low-power crystal oscillator for RF tuner

A 37. 5 MHz differential complementary metal oxide semiconductor （CMOS） crystal oscillator with low power and low phase noise for the radio frequency tuner of digital radio broadcasting digital radio mondiale （DRAM） and digital audio broadcasting （DAB） systems is realized and characterized. The conventional cross-coupled n-type metal oxide semiconductor （NMOS） transistors are replaced by p-type metal oxide semiconductor （PMOS） transistors to decrease the phase noise in the core part of the crystal oscillator. A symmetry structure of the current mirror is adopted to increase the stability of direct current. The amplitude detecting circuit made up of a single- stage CMOS operational transconductance amplifier （OTA） and a simple amplitude detector is used to improve the current accuracy of the output signals. The chip is fabricated in a 0. 18- pxn CMOS process, and the total chip size is 0. 35 mm x 0. 3 mm. Under a supply voltage of 1.8 V, the measured power consumption is 3.6 mW including the output buffer for 50 testing loads. The proposed crystal oscillator exhibits a low phase noise of - 134. 7 dBc/Hz at 1-kHz offset from the center frequency of 37. 5 MHz.

A 2.4GHz Quadrature Output Frequency Synthesizer

A design and implementation for a 2.4GHz quadrature output frequency synthesizer intended for bluetooth in 0. 35μm CMOS technology are presented. A differentially controlled quadrature voltage-controlled oscillator （QVCO） is employed to generate quadrature （I/Q） signals. A second-order loop filter, with a unit gain transconductance amplifier having the performance of a third-order loop filter,is exploited for low cost. The measured spot phase noise is -106.15dBc/Hz@ 1MHz. Close-in phase noise is less than -70dBc/Hz. The synthesizer consumes 13.5mA under a 3.3V voltage supply. The core size is 1.3mm×0. 8mm.

Wideband CMOS LC VCO design and phase noise analysis

A wideband LC cross-coupled voltage controlled oscillator（VCO） is designed and realized with standard 0. 18 μm complementary metal-oxide-semiconductor（CMOS） technology. Band switching capacitors are adopted to extend the frequency tuning range, and the phase noise is optimized in the design procedure. The functional relationships between the phase noise and the transistors＇ width-length ratios are deduced by a linear time variant （LTV） model. The theoretical optimized parameter value ranges are determined. To simplify the calculation, the working region is split into several sub-ranges according to transistor working conditions. Thus, a lot of integrations are avoided, and the phase noise function upon the design variables can be expressed as simple proportion formats. Test results show that the DC current is 8.8 mA under a voltage supply of 1.8 V; the frequency range is 1.17 to 1.90 GHz, and the phase noise reaches - 83 dBc/Hz at a 10 kHz offset from the carrier. The chip size is 1. 2 mm × 0. 9 mm.

A 2GHz Low Power Differentially Tuned CMOS Monolithic LC-VCO

A 2GHz differentially tuned CMOS monolithic LC-VCO is designed and fabricated in a 0.18μm CMOS process. The VCO has a 16.15% tuning range （from 1. 8998 to 2. 2335GHz） through a combination of analog and digital tuning techniques （4-bit binary switch-capacitor array）. The measured phase noise is - 118.17dBc/Hz at a 1MHz offset from a 2. 158GHz carrier. With the presented improved switch,the phase noise varies no more than 3dB at different digital control bits. The phase noise changes only by about 2dB in the tuning range because of the pn-junctions as the varactors. The VCO draws a current of about 2. lmA from a 1.8V power supply and works normally with a 1.5V power supply.

A 5-Gbit/s monolithically-integrated low-power clock recovery circuit in 0.18-μm CMOS

In order to make a 10 Gbit/s 2：1 half-rate multiplexer operate without external clocks, a 5 Gbit/s clock recovery （CR） circuit is needed to extract the desired clock from one input data. For the CR circuit, a 3-stage ring voltage-controlled oscillator （VCO） is employed to avoid an unreliable startup of a 2-stage VCO and a low oscillation frequency of a 4-stage VCO. A phase frequency detector （PFD） is used to expand the pull-in range to meet the wide tuning range of a VCO required by process-voltage-temperature （PVT） variation. SMIC 0. 18-μm CMOS technology is adopted and the core area is 170 μm ×270 μm. Measurements show that, under a 1.8 V supply voltage, it consumes only about 90 mW, and has an input sensitivity of less than 25 mV, an output single-ended swing of above 300 mV, a phase noise of - 114 dBc/Hz at 1 MHz offset and a pull-in range of 1 GHz.

Low Phase Noise Quadrature Oscillators Using New Injection Locked Technique

A low phase noise quadrature oscillator using the new injection locked technique is proposed. The incident signal is directly injected into the common-source connection of the sub-harmonic oscillator. In principle, the phase noise performance of the quadrature output is better than the sub-harmonic oscillator itself. The quadrature oscillator is implemented in a 0. 25μm CMOS process. Measurements show the proposed oscillator could achieve a phase noise of --130dBc/Hz at 1MHz offset from 1. 13GHz carrier while only drawing an 8.0mA current from the 2.5V power supply.

Design of a 2.5GHz Low Phase-Noise LC-VCO in 0.35μm SiGe BiCMOS

This paper introduces a 2.5GHz low phase-noise cross-coupled LC-VCO realized in 0.35μm SiGe BiCMOS technology. The conventional definition of a VCO operating regime is revised from a new perspective. Analysis shows the importance of inductance and bias current selection for oscillator phase noise optimization. Differences between CMOS and BJT VCO design strategy are then analyzed and the conclusions are summarized. In this implementation, bonding wires form the resonator to improve the phase noise performance. The VCO is then integrated with other components to form a PLL frequency synthesizer with a loop bandwidth of 30kHz. Measurement shows a phase noise of - 95dBc/Hz at 100kHz offset and - 116dBc/Hz at 1MHz offset from a 2.5GHz carrier. At a supply voltage of 3V, the VCO core consumes 8mA. To our knowledge,this is the first differential cross-coupled VCO in SiGe BiCMOS technology in China.

Low phase noise LC VCO design in CMOS technology

This paper presents the design and the experimental measurements of two complementary metal-oxide-semiconductor (CMOS) LC-tuned voltage controlled oscillators (VCO) implemented in a 0.18 μm 6-metal-layer mixed-signal/RF CMOS technology. The design methodologies and approaches for the optimization of the ICs are presented. The first design is optimized for mixed-signal transistor, oscillated at 2.64 GHz with a phase noise of -93.5 dBc/Hz at 500 kHz offset. The second one optimized for RF transistor, using the same architecture, oscillated at 2.61 GHz with a phase noise of -95.8 dBc/Hz at 500 kHz offset. Under a 2 V supply, the power dissipation is 8 mW, and the maximum buffered output power for mixed-signal and RF transistor are -7 dBm and -5.4 dBm, respectively. Both kinds of oscillators make use of on-chip components only, allowing for simple and robust integration.

Frequency synthesizer for DRM/DAB/AM/FM RF front-end

This paper describes a wideband low phase noise frequency synthesizer.It operates in the multi-band including digital radio mondiale DRM digital audio broadcasting DAB amplitude modulation AM and frequency modulation FM .In order to cover the signals of the overall frequencies a novel frequency planning and a new structure are proposed. A wide-band low-phase-noise low-power voltage-control oscillator VCO and a high speed wide band high frequency division ratio pulse swallow frequency divider with a low power consumption are presented.The monolithic DRM/DAB/AM/FM frequency synthesizer chip is also fabricated in a SMIC＇s 0.18-μm CMOS process.The die area is 1 425 μm ×795 μm including the test buffer and pads. The measured results show that the VCO operating frequency range is from 2.22 to 3.57 GHz the measured phase noise of the VCO is 120.22 dBc/Hz at 1 MHz offset the pulse swallow frequency divider operation frequency is from 0.9 to 3.4 GHz.The phase noise in the phase-locked loop PLL is-59.52 dBc/Hz at 10 kHz offset and fits for the demand of the DRM/DAB/AM/FM RF front-end. The proposed frequency synthesizer consumes 47 mW including test buffer under a 1.8 V supply.

Design of a 4.224GHz Quadrature LC-VCO

A 4. 224GHz quadrature voltage-controlled oscillator （QVCO） applied in MB-OFDM UWB synthesizers is implemented in 0.18μm RF-CMOS technology. An improved structure of the QVCO is presented for better phase noise. A novel configuration of a MOS varactor is designed for good linearity of K as well as a new digital capacitor controlled array topology with lower parasitic capacitance and lower Ron. Measurement results show a phase noise of - 90.4dBc/Hz at 100kHz offset and - 116.7dBc/Hz at 1MHz offset from a carrier close to 4. 224GHz. The power dissipation is 10. 55mW from a 1.8V supply.