A 6.25 Gbps SerDes core used in the high signed based on the OIF-CEI-02.0 standard. To speed backplane communication receiver has been decounteract the serious Inter-Syrmbol-Interference （ISI）, the core employed a h...A 6.25 Gbps SerDes core used in the high signed based on the OIF-CEI-02.0 standard. To speed backplane communication receiver has been decounteract the serious Inter-Syrmbol-Interference （ISI）, the core employed a half-rate four-tap decision feedback equalizer （DFE）. The equalizer used the Signsign least mean-squared （SS-LMS） algorithm to realize the coefficient adaptation. An automatic gain control （AGC） amplifier with the sign least mean-squared （S-LMS） algorithm has been used to compensate the transmission media loss. To recover the clock signal from the input data serial and provide for the DFE and AGC, a bang-bang clock recovery （BB-CR） is adopted. A third order phase loop loek （PLL） model was proposed to predict characteristics of the BB-CR. The core has been verified by behavioral modeling in MATLAB. The results indicate that the core can meet the specifications of the backplane receiver. The DFE recovered data over a 34＂ FR-4 backplane has a peak-to-peak jitter of 17 ps, a horizontal eye opening of 0.87 UI, and a vertical eye opening of 500 mVpp.展开更多
A CMOS dual-band low noise amplifer (LNA) design is presented.The purpose of th is work is intended to substitute only one LNA for two individual LNA's in dual -band transceivers for applications such as wireless ...A CMOS dual-band low noise amplifer (LNA) design is presented.The purpose of th is work is intended to substitute only one LNA for two individual LNA's in dual -band transceivers for applications such as wireless local area network complying with both IEEE 802.11a and 802.11b/g.Dua l-band simultaneous input power and noise matching and load shaping are discuss ed.The chip is implemented in 0.25μm CMOS mixed and RF process.The measured pe rformance is summarized and discussed.展开更多
This paper presents a new Transmitted Reference (TR) Ultra-WideBand (UWB) receiver based on Spatial Diversity (SD), which employs Multi-Antenna Technology (MAT) to improve the performance of TR-UWB receiver. According...This paper presents a new Transmitted Reference (TR) Ultra-WideBand (UWB) receiver based on Spatial Diversity (SD), which employs Multi-Antenna Technology (MAT) to improve the performance of TR-UWB receiver. According to the amplitude of correlator output of every antenna branch, this paper analyzed the performances of the proposed TR-UWB receiver employing three different kinds of combination strategies, i.e., Maximum Ratio Combination (MRC), Equal Gain Combination (EGC), and Selective Combination (SC), which are different from conventional ones, and theoretically proved that the performance of EGC is better than MRC. Simulation results verify that when EGC is adopted and BER=10-3, increasing three antennas provides Signal to Noise Ratio (SNR) gain of about 3 dB in CM4 channel and SNR gain of about 2 dB in CM2 channel.展开更多
This paper presents an innovative switched-mode auto gain control （AGC） circuit with internally created reset module for DC-10Mb/s burst-mode unbalanced （BMU） optical data transmission. Conventional AGC circuit is...This paper presents an innovative switched-mode auto gain control （AGC） circuit with internally created reset module for DC-10Mb/s burst-mode unbalanced （BMU） optical data transmission. Conventional AGC circuit is inappropriate for BMU data transmission because it is based on average level detection and requires considerable time to settle on a predefined gain. Therefore, we adopt a fast switched-mode AGC based on peak level detection. After the gain is adjusted, the peak level detectors need to re-detect the peak level of the input signal. Thus, we develop an internally created reset module. This AGC with reset module exhibits a fast operation and achieves an adjusted stable gain within one-bit, avoiding any bit loss up to 10Mb/s data rate. During power-up, the peak level detectors possibly hold an uncertain level resulting in the bit-errors. We propose a power-up reset circuit to solve this problem. Designed in a 0.5μm CMOS technology, the circuit achieves an optical sensitivity of better than -30dBm and a wide dynamic range of over 30dB with a power dissipation of only 30 mW from a 5V supply.展开更多
In order to meet the requirements for zero value stability of direct sequence spread spectrum(DSSS) signal processing in high dynamic scenario,digital automatic gain control(AGC) is employed to regulate power.However,...In order to meet the requirements for zero value stability of direct sequence spread spectrum(DSSS) signal processing in high dynamic scenario,digital automatic gain control(AGC) is employed to regulate power.However,conventional AGC causes degradation in the synchronization performance of DSSS receiver.Based on the theoretical analysis of the influence of digital AGC on DSSS signal synchronization,this paper proposes a new AGC algorithm,which is applicable to multi-channel digital DSSS signal receiver.By making power adjustment cycle and synchronization cycle coherent with each other adaptively,the influence of digital AGC on subsequent synchronization processing has been eliminated.Theoretical analysis,simulation results and experimental data verify the validity of the proposed algorithm.By virtue of the proposed algorithm,the influence of digital AGC on DSSS signal synchronization is eliminated.This algorithm applies to an aerospace engineering project successfully.展开更多
基金Supported by the High Technology Research and Development Programme of China (No. 2003AA31g030).
文摘A 6.25 Gbps SerDes core used in the high signed based on the OIF-CEI-02.0 standard. To speed backplane communication receiver has been decounteract the serious Inter-Syrmbol-Interference （ISI）, the core employed a half-rate four-tap decision feedback equalizer （DFE）. The equalizer used the Signsign least mean-squared （SS-LMS） algorithm to realize the coefficient adaptation. An automatic gain control （AGC） amplifier with the sign least mean-squared （S-LMS） algorithm has been used to compensate the transmission media loss. To recover the clock signal from the input data serial and provide for the DFE and AGC, a bang-bang clock recovery （BB-CR） is adopted. A third order phase loop loek （PLL） model was proposed to predict characteristics of the BB-CR. The core has been verified by behavioral modeling in MATLAB. The results indicate that the core can meet the specifications of the backplane receiver. The DFE recovered data over a 34＂ FR-4 backplane has a peak-to-peak jitter of 17 ps, a horizontal eye opening of 0.87 UI, and a vertical eye opening of 500 mVpp.
文摘A CMOS dual-band low noise amplifer (LNA) design is presented.The purpose of th is work is intended to substitute only one LNA for two individual LNA's in dual -band transceivers for applications such as wireless local area network complying with both IEEE 802.11a and 802.11b/g.Dua l-band simultaneous input power and noise matching and load shaping are discuss ed.The chip is implemented in 0.25μm CMOS mixed and RF process.The measured pe rformance is summarized and discussed.
文摘This paper presents a new Transmitted Reference (TR) Ultra-WideBand (UWB) receiver based on Spatial Diversity (SD), which employs Multi-Antenna Technology (MAT) to improve the performance of TR-UWB receiver. According to the amplitude of correlator output of every antenna branch, this paper analyzed the performances of the proposed TR-UWB receiver employing three different kinds of combination strategies, i.e., Maximum Ratio Combination (MRC), Equal Gain Combination (EGC), and Selective Combination (SC), which are different from conventional ones, and theoretically proved that the performance of EGC is better than MRC. Simulation results verify that when EGC is adopted and BER=10-3, increasing three antennas provides Signal to Noise Ratio (SNR) gain of about 3 dB in CM4 channel and SNR gain of about 2 dB in CM2 channel.
基金Supported by the Natural Science Foundation of Jiangsu Province （ BK2010411 ） and the National International Cooperation Project of China-Korea （2011DFA11310）.
文摘This paper presents an innovative switched-mode auto gain control （AGC） circuit with internally created reset module for DC-10Mb/s burst-mode unbalanced （BMU） optical data transmission. Conventional AGC circuit is inappropriate for BMU data transmission because it is based on average level detection and requires considerable time to settle on a predefined gain. Therefore, we adopt a fast switched-mode AGC based on peak level detection. After the gain is adjusted, the peak level detectors need to re-detect the peak level of the input signal. Thus, we develop an internally created reset module. This AGC with reset module exhibits a fast operation and achieves an adjusted stable gain within one-bit, avoiding any bit loss up to 10Mb/s data rate. During power-up, the peak level detectors possibly hold an uncertain level resulting in the bit-errors. We propose a power-up reset circuit to solve this problem. Designed in a 0.5μm CMOS technology, the circuit achieves an optical sensitivity of better than -30dBm and a wide dynamic range of over 30dB with a power dissipation of only 30 mW from a 5V supply.
基金support of the National High Technology Research and Development Program of China(863)(Grant No.2013AA1548)
文摘In order to meet the requirements for zero value stability of direct sequence spread spectrum(DSSS) signal processing in high dynamic scenario,digital automatic gain control(AGC) is employed to regulate power.However,conventional AGC causes degradation in the synchronization performance of DSSS receiver.Based on the theoretical analysis of the influence of digital AGC on DSSS signal synchronization,this paper proposes a new AGC algorithm,which is applicable to multi-channel digital DSSS signal receiver.By making power adjustment cycle and synchronization cycle coherent with each other adaptively,the influence of digital AGC on subsequent synchronization processing has been eliminated.Theoretical analysis,simulation results and experimental data verify the validity of the proposed algorithm.By virtue of the proposed algorithm,the influence of digital AGC on DSSS signal synchronization is eliminated.This algorithm applies to an aerospace engineering project successfully.
