代替高频信号源的石英晶体控频振荡器

在电路与信号系统实验中的<信号频谱测试及信号通过谐振回路>实验项目,该实验涉及较多的仪器,其中,高频信号发生器利用率较低,只用其450kHz正弦信号作为载波信号用,为节约经费,我们制作了22个石英晶体控频振荡器,产生450kHz1.5V左右电压的正弦信号,供实验用,代替了原来的XFG-7高频信号源。实验效果很好,每个晶体控频振荡器成本仅20元左右,又便于维护。现将它介绍如下。

高频宽频偏压控晶体振荡器

详细介绍了高频宽频偏压控晶体振荡器的工作原理，根据技术指标给出了实际电路，并对电路进行了分析，最后给出测试结果。

Wideband CMOS LC VCO design and phase noise analysis

A wideband LC cross-coupled voltage controlled oscillator（VCO） is designed and realized with standard 0. 18 μm complementary metal-oxide-semiconductor（CMOS） technology. Band switching capacitors are adopted to extend the frequency tuning range, and the phase noise is optimized in the design procedure. The functional relationships between the phase noise and the transistors＇ width-length ratios are deduced by a linear time variant （LTV） model. The theoretical optimized parameter value ranges are determined. To simplify the calculation, the working region is split into several sub-ranges according to transistor working conditions. Thus, a lot of integrations are avoided, and the phase noise function upon the design variables can be expressed as simple proportion formats. Test results show that the DC current is 8.8 mA under a voltage supply of 1.8 V; the frequency range is 1.17 to 1.90 GHz, and the phase noise reaches - 83 dBc/Hz at a 10 kHz offset from the carrier. The chip size is 1. 2 mm × 0. 9 mm.

Fast-Lock Low-Jitter PLL with a Simple Phase-Frequency Detector

A fast-locking, low-jitter, phase-locked loop （PLL） with a simple phase-frequency detector is proposed. The phase-frequency detector is composed of only two XOR gates. It simultaneously achieves low jitter and short locking time. The voltage-controlled oscillator within the PLL consists of four-stage ring oscillators which are coupled to each other and oscillate with the same frequency and a phase shift of 45. The PLL is fabricated in 0. 1Stem CMOS technology. The measured phase noise of the PLL output at 500kHz offset from the 5GHz center frequency is - 102.6dBc/Hz. The circuit exhibits a capture range of 280MHz and a low RMS jitter of 2.06ps. The power dissipation excluding the output buffers is only 21.6roW at a 1.8V supply.

A Low Jitter PLL in a 90nm CMOS Digital Process

A low jitter phase-locked loop （PLL） that does not need analog resistors and capacitors is designed and fabrica- ted in a 90nm CMOS digital process. The metal parasitic capacitor is used in the PLL loop filter. Test results show that when the PLL is locked on 1. 989GHz, the RMS jitter is 3. 7977ps, the peak-to-peak jitter is 31. 225ps, and the power con- sumption is about 9mW. The locked output frequency range is from 125MHz to 2.7GHz.

Integrated Low-Power CMOS VCO and Its Divide-by-2 Dividers

An integrated low power CMOS VCO and its divide by 2 dividers for WLAN transceivers are presented.The VCO is based on on chip symmetrical spiral inductor and differential diode and the divide by 2 dividers are based on the ILFD technique.Due to differential LC tanks and ILFD techniques,power consumption is low.The circuit is implemented in a 0 18μm CMOS process.Measurements show the proposed circuit could produce 3 6/1 8GHz dual band LO signals with a wide tuning range and low phase noise.1 8GHz LO signals are quadrature.It consumes 5mA at V DD =1 5V.The size of die area is only 1 0mm×1 0mm.

Low phase noise LC VCO design in CMOS technology

This paper presents the design and the experimental measurements of two complementary metal-oxide-semiconductor (CMOS) LC-tuned voltage controlled oscillators (VCO) implemented in a 0.18 μm 6-metal-layer mixed-signal/RF CMOS technology. The design methodologies and approaches for the optimization of the ICs are presented. The first design is optimized for mixed-signal transistor, oscillated at 2.64 GHz with a phase noise of -93.5 dBc/Hz at 500 kHz offset. The second one optimized for RF transistor, using the same architecture, oscillated at 2.61 GHz with a phase noise of -95.8 dBc/Hz at 500 kHz offset. Under a 2 V supply, the power dissipation is 8 mW, and the maximum buffered output power for mixed-signal and RF transistor are -7 dBm and -5.4 dBm, respectively. Both kinds of oscillators make use of on-chip components only, allowing for simple and robust integration.

Key technologies of frequency-hopping frequency synthesizer for Bluetooth RF front-end

A scheme of a frequency-hopping frequency-synthesizer applied to a Bluetooth ratio frequency （RF） front-end is presented,and design of a voltage controlled oscillator （VCO） and dual-modulus prescaler are focused on.It is fabricated in a 0.18 μm mixed-signal CMOS （complementary metal-oxide-semiconductor transistor） process.The power dissipation of VCO is low and a stable performance is gained.The measured phase noise of VCO at 2.4 GHz is less than -114.32 dBc/Hz.The structure of the DMP is optimized and a novel D-latch integrated with ＂OR＂ logic gate is used.The measured results show that the chip can work well under a 1.8 V power supply.The power dissipation of the core part in a dual modulus prescaler is only 5.76 mW.An RMS jitter of 2 ps is measured on the output signal at 118.3 MHz.It is less than 0.02% of the clock period.

A Fractional-N CMOS DPLL with Self-Calibration

A digital phase-locked loop （DPLL） based on a new digital phase-frequency detector is presented. The self-calibration technique is employed to acquire wide lock range,low jitter, and fast acquisition. The DPLL works from 60 to 600MHz at a supply voltage of 1.8V. It also features a fraetional-N synthesizer with digital 2nd-order sigma-delta noise shaping, which can achieve a short lock time,a high frequency resolution,and an improved phase-noise spectrum. The DPLL has been implemented in SMIC 0. 18μm 1.8V 1P6M CMOS technology. The peak-to-peak jitter is less than 0. 8% of the output clock period and the lock time is less than 150 times of the reference clock period after the pre-divider.

Frequency synthesizer for DRM/DAB/AM/FM RF front-end

This paper describes a wideband low phase noise frequency synthesizer.It operates in the multi-band including digital radio mondiale DRM digital audio broadcasting DAB amplitude modulation AM and frequency modulation FM .In order to cover the signals of the overall frequencies a novel frequency planning and a new structure are proposed. A wide-band low-phase-noise low-power voltage-control oscillator VCO and a high speed wide band high frequency division ratio pulse swallow frequency divider with a low power consumption are presented.The monolithic DRM/DAB/AM/FM frequency synthesizer chip is also fabricated in a SMIC＇s 0.18-μm CMOS process.The die area is 1 425 μm ×795 μm including the test buffer and pads. The measured results show that the VCO operating frequency range is from 2.22 to 3.57 GHz the measured phase noise of the VCO is 120.22 dBc/Hz at 1 MHz offset the pulse swallow frequency divider operation frequency is from 0.9 to 3.4 GHz.The phase noise in the phase-locked loop PLL is-59.52 dBc/Hz at 10 kHz offset and fits for the demand of the DRM/DAB/AM/FM RF front-end. The proposed frequency synthesizer consumes 47 mW including test buffer under a 1.8 V supply.

A 5-Gbit/s monolithically-integrated low-power clock recovery circuit in 0.18-μm CMOS

In order to make a 10 Gbit/s 2：1 half-rate multiplexer operate without external clocks, a 5 Gbit/s clock recovery （CR） circuit is needed to extract the desired clock from one input data. For the CR circuit, a 3-stage ring voltage-controlled oscillator （VCO） is employed to avoid an unreliable startup of a 2-stage VCO and a low oscillation frequency of a 4-stage VCO. A phase frequency detector （PFD） is used to expand the pull-in range to meet the wide tuning range of a VCO required by process-voltage-temperature （PVT） variation. SMIC 0. 18-μm CMOS technology is adopted and the core area is 170 μm ×270 μm. Measurements show that, under a 1.8 V supply voltage, it consumes only about 90 mW, and has an input sensitivity of less than 25 mV, an output single-ended swing of above 300 mV, a phase noise of - 114 dBc/Hz at 1 MHz offset and a pull-in range of 1 GHz.

Key Techniques of Frequency Synthesizer for WLAN Receivers

Several key techniques for a PLL-type frequency synthesizer for WLAN receivers are studied. Its structure is analyzed and the main parameters are proposed. A monolithic LC-tuned voltage controlled oscillator （LCVCO） with low phase noise is fabricated with TSMC 0.18μm RF （radio frequency） CMOS technology. The measured phase noise is - ll7dBc/Hz at 4MHz off the center frequency of 4. 189GHz. A down-scaling circuit with low power dissipation was fabricated in a TSMC 0.18μm mixed-signal CMOS process. The measured results show that the IC can work well under a 1.8V power supply. Its total power dissipation is only 13mW.

Digital Coarse Tuning Loop for Wide-Band Fast-Settling Dual-Loop Frequency Synthesizers

A new coarse tuning loop for a wide-band dual-loop frequency synthesizer is presented. The coarse tuning structure is composed of two digital modules, including a successive approximation register and a frequency comparator with a novel structure. The frequency comparator counts the prescaler cycles within a certain reference time and compares the number with preset data to estimate the VCO frequency. The frequency comparison error is analyzed in detail. Within a given coarse tuning time,our proposed structure shows a comparison error 20 times smaller than that of other reported structures. This structure also reuses the programmable divider as a part of the coarse tuning loop so that the circuit is greatly simplified.

A 5-GHz frequency synthesizer with constant bandwidth for low IF ZigBee transceiver applications

A fully integrated integer-N frequency synthesizer is implemented.The synthesizer is designed for low intermediate frequency （IF）ZigBee transceiver applications.Techniques used to make the loop bandwidth constant across the whole output frequency range of the voltage controlled oscillator（VCO）are adopted to maintain phase noise optimization and loop stability.In-phase and quadrature（IQ）signals are generated by a 1/2 frequency divider at the output of the VCO.The synthesizer is fabricated in 0.18 μm radio frequency（RF） complementary metal oxide semiconductor transistor （CMOS）technology.The chip area is 1.7 mm2.The synthesizer is measured on wafer.It consumes totally 28.8 mW excluding output buffers from a supply voltage of 1.8 V.The measured phase noise is -110 and -122 dBc/Hz at the offset of 1 and 3 MHz from a 2.405 GHz carrier,respectively.The measured reference spur at a 2 MHz offset from a 2.405 GHz carrier is-48.2 dBc.The measured setting time of the synthesizer is about 160 μs.

Coordinated and uncoordinated design of LFO damping controllers with IPFC and PSS using ICA and SFLA

A single machine-infinite-bus(SMIB) system including the interline power flow controllers(IPFCs) and the power system stabilizer(PSS) controller is addressed. The linearized system model is considered for investigating the interactions among IPFC and PSS controllers. To improve the stability of whole system again different disturbances, a lead-lag controller is considered to produce supplementary signal. The proposed supplementary controller is implemented to improve the damping of the power system low frequency oscillations(LFOs). Imperialist optimization algorithm(ICA) and shuffled frog leaping algorithm(SFLA) are implemented to search for optimal supplementary controllers and PSS parameters. Moreover, singular value decomposition(SVD) method is utilized to select the most effective damping control signal of IPFC lead-lag controllers. To evaluate the system performance, different operating conditions are considered. Reponses of system in five modes including uncoordinated and coordinated modes of IPFC and PSS using ICA and SFLA are studied and compared. Considering the results, response of system without controller shows the highest overshoot and the longest settling time for rotor angel at the different operating conditions. In this mode of system, rotor speed has the highest overshoot. Rotor angel in the system with only PSS includes lower overshoot and oscillation than system without controller. When PSS is only implemented, rotor speed deviation has the longest settling time. Rotor speed deviation in the uncoordinated mode of IPFC and PSS shows lower overshoot than system with only PSS and without controller. It is noticeable that in this mode, rotor angel has higher overshoot than system with only PSS. The superiority of the suggested ICA-based coordinated controllers is obvious compared with SFLA-based coordinated controllers and other system modes. Responses of coordinated PSS and IPFC SFLA-based supplementary controllers include higher peak amplitude and longer settling time compared with coordinated IPFC and PSS ICA-based controllers. This comparison shows that overshoots, undershoots and the settling times are reduced considerably in coordinated mode of IPFC based controller and PSS using ICA. Analysis of the system performance shows that the proposed method has excellent response to different faults in power system.

Design of 1GHz Local Oscillator with DLL -Based Frequency Multiplier Technique

A new method of synthesizing 1GHz based on a 0 5μm CMOS D LL is proposed,which can synthesize frequency with simple logic and amplifiers.T he designed frequency synthesizer consists of a DLL (Delay-Locked Loop) and a b uilding block of synthesizing logic.The reference frequency input into this freq uency synthesizer is 25MHz and the synthesized frequency is 1GHz.

Research on CMOS Mm-Wave Circuits and Systems for Wireless Communications

This paper lenges in the design of discusses some chal- millimeter-wave （mln- wave） circuits and systems for 5th generation （5G） wireless systems in CMOS process. The properties of some passive and active devices such as inductors, capacitors, transmission lines, translbrmers and transistors in mm-wave frequency band are discussed. Self-healing technique dealing with PVT variation, res- onant mode switching technique to enhance frequency tuning range of voltage controlled oscillator （VCO） and dual mode technique for power amplifier （PA） efficiency enhancement are introduced. At last, A fully-integrated 60 GHz 5 Gb/s QPSK transceiver with the transmit/receive （T/R） switch in 65nm CMOS process is introduced. The measured error vector magnitude （EVM） of the TX is -21.9 dB while the bit error rate （BER） of the RX with a -52 dBm sine-wave input is below 8e-7 when transmitting/receiving 5 Gb/s data. The transceiver is powered by 1.0 V and 1.2 V supply （except the phase-frequency detector and charge-pump in the frequency synthesizer which are powered by 2.5 V supply） and con- sumes 135 mW in TX mode and 176 mW in RX mode.

A Low Power Dissipation Wide-Band CMOS Frequency Synthesizer for a Dual-Band GPS Receiver

This paper presents a wide tuning range CMOS frequency synthesizer for a dual-band GPS receiver,which has been fabricated in a standard 0.18μm RF CMOS process. With a high Q on-chip inductor, the wide-band VCO shows a tuning range from 2 to 3.6GHz to cover 2.45 and 3.14GHz in case of process corner or temperature variation,with a current consumption varying accordingly from 0.8 to 0.4mA,from a 1.8V supply voltage. Measurement results show that the whole frequency synthesizer consumes very low power of 5.6mW working at L1 band with in-band phase noise less than - 82dBc/Hz and out-of-band phase noise about - ll2dBc/Hz at 1MHz offset from a 3. 142GHz carrier. The performance of the frequency synthesizer meets the requirements of GPS applications very well.