Architecture design of GPS software receiver and implementation of its acquisition algorithm with fine frequency estimation

The design of a global positioning system （GPS） software receiver is introduced. This design uses the concept of software radio, and it consists of the following parts： front-end, acquisition, tracking, synchronization, navigation solution and some assisting modules. In the acquisition module, the acquisition algorithm based on circular correlation is utilized. The input data and the local code are converted into the frequency domain by means of the fast Fourier transform （FFT）. After performing circular correlation, the initial phase of the C/A code can be obtained and the cartier frequency can be found in 1 kHz frequency resolution, which is too coarse to use for the tracking loop. In order to improve the frequency resolution, the fine frequency estimation through a phase relationship is then achieved, by which, the frequency resolution is improved dramatically. Experiments show that the inaccuracy of the carrier frequency can be estimated within a few hertz by the fine frequency estimation method, and the fine frequency attained can be directly used for the tracking loop.

Concept and Design of a Novel High-Bandwidth,High-Sensitivity Differential Receiver for Optical Interconnections

A novel high-bandwidth, high-sensitivity differential optical receiver without any additional cost compared to general optical receivers, is proposed for high-speed optical communications and interconnections. High bandwidth and high sensitivity are achieved through a fully differential transimpedance amplifier with balanced input loads and two photodetectors to convert the incident light into a pair of differential photogenerated currents,respectively. In addition,a corresponding 0.35μm standard CMOS optoelectronic integrated receiver with two 60μm × 30μm, 1. 483pF fingered p^＋/n- well/p-substrate photodiodes is also presented. The simulation results demonstrate that it achieves a 1.37GHz bandwidth and a 81.9dBΩ transimpedance gain,supporting data rates up to at least 2Gbit/s. The device consumes a core area of 0. 198mm^2 and the optical sensitivity is at least - 13dBm for a 10^-12 bit error rate under a 2^15 - 1 PRBS input signal.

Design and Implementation of an Optoelectronic Integrated Receiver in Standard CMOS Process

A wideband monolithic optoelectronic integrated receiver with a high-speed photo-detector,completely compatible with standard CMOS processes,is designed and implemented in 0.6μm standard CMOS technology.The experimental results demonstrate that its performance approaches applicable requirements,where the photo-detector achieves a -3dB frequency of 1.11GHz,and the receiver achieves a 3dB bandwidth of 733MHz and a sensitivity of -9dBm for λ=850nm at BER=10-12.

A 1.8V CMOS Direct Conversion Receiver for a 900MHz RFID Reader Chip

A direct conversion receiver with optimized tolerance to local carrier interference is designed and implemented in a 0.18μm 1P6M mixed-signal CMOS process for a 900MHz RFID reader transceiver. A baseband amplifier with series feedback topology is proposed to achieve passive mixer buffering,baseband DC cancellation,and signal amplification simultaneously. The receiver has a measured input ldB compression point of - 4dBm and a sensitivity of - 70dBm when 10dB SNR for digital demodulation is required. The receiver is integrated in a reader transceiver chip and consumes 90mA from a 1.8V supply.

On simulation of precise orbit determination of HY-2 with centimeter precision based on satellite-borne GPS technique

The HY-2 satellite carrying a satellite-borne GPS receiver is the first Chinese radar altimeter satellite, whose radial orbit determination precision must reach the centimeter level. Now HY-2 is in the test phase so that the observations are not openly released. In order to study the precise orbit determination precision and procedure for HY-2 based on the satellite- borne GPS technique, the satellite-borne GPS data are simulated in this paper. The HY-2 satellite-borne GPS antenna can receive at least seven GPS satellites each epoch, which can validate the GPS receiver and antenna design. What＇s more, the precise orbit determination processing flow is given and precise orbit determination experiments are conducted using the HY-2-borne GPS data with both the reduced-dynamic method and the kinematic geometry method. With the 1 and 3 mm phase data random errors, the radial orbit determination precision can achieve the centimeter level using these two methods and the kinematic orbit accuracy is slightly lower than that of the reduced-dynamic orbit. The earth gravity field model is an important factor which seriously affects the precise orbit determination of altimeter satellites. The reduced-dynamic orbit determination experiments are made with different earth gravity field models, such as EIGEN2, EGM96, TEG4, and GEMT3. Using a large number of high precision satellite-bome GPS data, the HY-2 precise orbit determination can reach the centimeter level with commonly used earth gravity field models up to above 50 degrees and orders.

Method of Jamming C/A Code GPS Receiver

The schemes and effects of electronically jamming GPS’s C/A code receivers are studied by using CW as the narrow band jamming signal and BPSK signal modulated by Gold code which is incoherent to that adopted by GPS as the wide band one. By simulating with Monte Carlo method and programming in Matlab language, the various jamming results in terms of bit error rate under several jamming scenarios are obtained. Through analyzing the simulation results and quantitative dependences of jamming effects on the distance from jammer to GPS receiver and the jammer’s height over ground, it is concluded that jamming with wide band jammer is much more effective than that with narrow band one.

2.5 Gbit/s monolithic ICs for optical fiber transmitter and receiver in 0.35 μm CMOS process

2.5 Gbit/s monolithic integrated circuits （ICs） for optical fiber transmitter and receiver in 0.35 μm CMOS （complementary metal-oxide-semiconductor transistor） process are presented. The transmitter, which includes a 4： 1 multiplexer and a laser diode driver （LDD）, has four 622 Mbit/s random signals as its inputs and gets a 2.5 Gbit/s driving signal as its output; the receiver detects a 2.5 Gbit/s random signal and gets four 622 Mbit/s signals at the output. The main circuits include a trans-impedance amplifier （TIA）, a limiting amplifier, a clock and data recovery （CDR） unit, and a 1： 4 demultiplexer （DEMUX）. Test results prove the logic functions of the transmitter to be right, and the 10% to 90% rise and fall times of transmitter＇s output data eye diagram are 211.1 ps and 200 ps, respectively. The sensitivity of the receiver is measured to be better than 20 mV. The root mean square jitter of the DEMUX＇s output data is 15.6 ps and that of the clock after 1： 4 frequency dividing is 1.9 ps. Two chips are both applicable to 2.5 Gbit/s optical fiber communication systems.

A High Speed,12-Channel Parallel,Monolithic Integrated CMOS OEIC Receiver

The design and fabrication of a high speed, 12-channel monolithic integrated CMOS optoelectronic integrated circuit （OEIC） receiver are reported. Each channel of the receiver consists of a photodetector, a transimpedance amplifier,and a post-amplifier. The double photodiode structure speeds up the receiver but hinders responsivity. The adoption of active inductors in the TIA circuit extends the - 3dB bandwidth to a higher level. The receiver has been realized in a CSMC 0.6μm standard CMOS process. The measured results show that a single channel of the receiver is able to work at bit rates of 0.8- 1.4Gb/s. Altogether, the 12-channel OEIC receiver chip can be operated at 15Gb/s.

A 10Gb/s GaAs PHEMT High Gain Preamplifier for Optical Receivers

A high gain cascade connected preamplifier for optical receivers is developed with 0.5μm GaAs PHEMT technology from the Nanjing Electronic Devices Institute. To begin with, the transimpedance amplifier has a -3dB bandwidth of 10GHz, with a small signal gain of around 9dB. The post-stage distributed amplifier （DA） has a -3dB bandwidth of close to 20GHz,with a small signal gain of around 12dB. As a whole,the cascade preamplifier has a measured small signal gain of 21.3dB and a transimpedance of 55.3dBΩ in a 50Ω system. With a higher signal-to-noise ratio than that of the TIA and a markedly improved waveform distortion compared with that of the DA, the measured output eye diagram for 10Gb/s NRZ pseudorandom binary sequence is clear and symmetric.

Sensitivity Design for a CMOS Optoelectronic Integrated Circuit Receiver

A sensitivity design method for a CMOS optoelectronic integrated circuit （OEIC） receiver is reported. The receiver consists of a regulated cascade （RGC） transimpedance amplifier （TIA） and a double photodiode （DPD） detector. The noise and sensitivity of the receiver are analyzed in detail. The noise mainly comes from the thermal noise of resistors and the flicker noise of MOSFETs. The relationship between noise and receiver sensitivity is presented. The sensitivity design method for the receiver is given by a set of equations. The OEIC receiver was implemented in a CSMC 0.6μm standard CMOS process. The measured eye diagram shows that the CMOS OEIC receiver is able to work at bit rates of up to 1.25GB/s and the sensitivity is - 12dBm.

Bandwidth Design for CMOS Monolithic Photoreceiver

A monolithic photoreceiver which consists of a double photodiode (DPD) detector and a regulated cascade (RGC) transimpedance amplifier (TIA) is designed.The small signal circuit model of DPD is given and the bandwidth design method of a monolithic photoreceiver is presented.An important factor which limits the bandwidth of DPD detector and the photoreceiver is presented and analyzed in detail.A monolithic photoreceiver with 1.71GHz bandwidth and 49dB transimpedance gain is designed and simulated by applying a low-cost 0.6μm CMOS process and the test result is given.

A Low Noise,High Linearity CMOS Receiver for 802.11b WLAN Applications

A 2.4GHz monolithic CMOS receiver with direct-conversion architecture is presented. This quadrature receiver is designed for 802.11b wireless LAN applications at the maximum data rate of 11Mbps as a low-cost solution. Five key blocks,i, e., a low noise amplifier （LNA）, a down-conversion mixer, a variable gain amplifier, a low pass filter, and a DC- offset cancellation circuit,are designed based on system design and low noise high linearity considerations. The necessary auxiliary circuits are also included. Fabricated in SMIC 0.18μm 1p6m RF CMOS process, the receiver＇s performance is measured as：4. 1 dB noise figure, - 7.5dBm input third order intercept point （IIP3） for LNA ＆ mixer at high gain setting, - 14dBm IIP3 for the whole receiver,53dBc @30MHz offset of adjacent channel power rejection,and less than 5mV out- put DC-offset. The receiver consumes 44mA under a 1.8V power supply with I,Q two paths.

Relationship Between Noise Figure and Equivalent Input Noise Current Spectral Density for Optical Receiver Design

Based on the equivalent circuit model of a two-port optical receiver front-end,the relationship between the equivalent input noise current spectral density and the noise figure is analyzed. The derived relationship has universal validity for determining the equivalent input noise current spectral density for optical receiver designs, as verified by measuring a 155Mb/s high-impedance optical receiver front.end. Good agreement between calculated and simulated results has been achieved.

Iterative receivers for SFBC-OFDM systems with adaptive training scheme

This paper considers the design of iterative receivers for space-frequencyblock-coded orthogonal frequency division multiplexing (SFBC-OFDM) systems in unknown wirelessdispersive fading channels. An iterative joint channel estimation and symbol detection algorithm isderived. In the algorithm, the channel estimator performs alternately in two modes. During thetraining mode, the channel state information (CSI) is obtained by a discrete-Fourier-transform-basedchannel estimator and the noise variance and covariance matrix of the channel response is estimatedby the proposed method. In the data transmission mode, the CSI and transmitted data is obtainediteratively. In order to suppress the error propagation caused by a random error in identifyingsymbols, a simple error propagation detection criterion is proposed and an adaptive training schemeis applied to suppress the error propagation. Both theoretical analysis and simulation results showthat this algorithm gives better bit-error-rate performance and saves the overhead of OFDM systems.

Monolithically Integrated Optoelectronic Receivers Implemented in 0.25μm MS/RF CMOS

A monolithically integrated optoelectronic receiver is presented. A silicon-based photo-diode and receiver circuits are integrated on identical substrates in order to eliminate the parasitics induced by hybrid packaging. Implemented in the present deep sub-micron MS/RF （mixed signal, radio frequency） CMOS,this monolithically OEIC takes advantage of several new features to improve the performance of the photo-diode and eventually the whole OEIC.

Model of the Rake Receiver for CDMA2000 Reverse Link

To improve performance of receiver, the pilot channel is added to reverse channels of CDMA2000 In this paper, the structure of reverse channels is outlined and the principle of Rake receiver is discussed, then the model of the Rake receiver is set up and some computer simulations are performed.

Performance Analysis of Fixed-Point Simulations on cdma2000-1x Downlink

Based on the physical layer standard of cdma2000, the performance analysis of fixed point simulations is presented in this paper on cdma2000 1x downlink. The effects of quantization and finite wordlength, which have typically been assumed negligible in floating point simulations, become significant for fixed point simulations. The complete fixed point simulation platform for cdma2000 1x downlink is developed by EDA tool - COSSAP. The structure and performance of the key component in cdma2000 systems, the RAKE receiver, are discussed in details. Comparisons of results between floating point and fixed point simulations lead to some important conclusions, which provide certain references for the implementation of practical systems.

SOLSM Channel Estimation for W CDMA

Estimation of Rayleigh fading channels using time multiplexed pilot symbols in W CDMA (FDD) is considered. Method of interpolation on a second order curve using the instantaneous channel estimation of two contiguous slots based on least square method (SOLSM) is presented. It is demonstrated by computer simulations that the channel distortion on data symbols in a slot can be estimated effectively compared to the method using simple linear interpolation, and the performance of the Rake combiner is improved effectively especially in fast moving cases.

A 0.5mV High Sensitivity 200Mbps CMOS Limiting Amplifier with RSSI for Optical Receivers

A 0. 5mV high sensitivity,200Mbps CMOS limiting amplifier （LA） with 72dB ultra wide dynamic range is described. A novel active DC offset cancellation loop is elaborately analyzed and designed to achieve this performance. Using a signal path, a received signal strength indicator （RSSI）, based on the piecewise-linear approximation, is realized with a ± 2dB logarithmic accuracy in a 60dB indicating range. The architecture of the LA and RSSI employed is determined by the optimal sensitivity and RSSI accuracy for a specified speed, gain, and power consumption. It consumes 60mW from a single 5V supply. The active area is 1.05mm^2 using standard 5V 0.6μm CMOS technology.