Novel schemes for a charge sensitive amplifier （CSA） and a CR-（RC）, semi-Gaussian shaper in a fully integrated CMOS readout circuit for particle detectors are presented. The CSA is designed with poly-resistors as ...Novel schemes for a charge sensitive amplifier （CSA） and a CR-（RC）, semi-Gaussian shaper in a fully integrated CMOS readout circuit for particle detectors are presented. The CSA is designed with poly-resistors as feedback components to reduce noise. Compared with conventional CSA, the input referred equivalent noise charge（ENC） is simulated to be reduced from 5036e to 2381e with a large detector capacitance of 150pF at the cost of 0.5V output swing loss. The CR-（RC）,semi-Gaussian shaper uses MOS transistors in the triode region in series with poly-resistors to compensate process variation without much linearity reduction.展开更多
A systematic approach is used to analyze the noise in CMOS low noise amplifier(LNA),including channel noise and induced gate noise in MOS devices.A new analytical formula for noise figure is proposed.Based on this for...A systematic approach is used to analyze the noise in CMOS low noise amplifier(LNA),including channel noise and induced gate noise in MOS devices.A new analytical formula for noise figure is proposed.Based on this formula,the impacts of distributed gate resistance and intrinsic channel resistance on noise performance are discussed.Two kinds of noise optimization approaches are performed and applied to the design of a 5 2GHz CMOS LNA.展开更多
For digital channelized frequency division multiple access based satellite communication(SATCOM) systems,it is a challenging but critical issue to improve the transponder power and spectrum efficiency simultaneously u...For digital channelized frequency division multiple access based satellite communication(SATCOM) systems,it is a challenging but critical issue to improve the transponder power and spectrum efficiency simultaneously under limited and non-linear high-power amplifier conditions.In this paper,different from the traditional link supportability designs aiming at minimizing the total transponder output power,a maximal sum Shannon capacity optimization objective is firstly raised subject to link supportability constraints.Furthermore,an efficient multilevel optimization(MO) algorithm is proposed to solve the considered optimization problem in the case of single link for each terminal.Moreover,in the case of multiple links for one terminal,an improved MO algorithm involving Golden section and discrete gradient searching procedures is proposed to optimize power allocation over all links.Finally,several numerical results are provided to demonstrate the effectiveness of our proposals.Comparison results show that,by the MO algorithm,not only all links' supportability can be guaranteed but also a larger sum capacity can be achieved with lower complexity.展开更多
Noise and linearity performances are critical characteristics for radio frequency integrated circuits (RFICs), especially for low noise amplifiers (LNAs). In this paper, a detailed analysis of noise and linearity for ...Noise and linearity performances are critical characteristics for radio frequency integrated circuits (RFICs), especially for low noise amplifiers (LNAs). In this paper, a detailed analysis of noise and linearity for the cascode architecture, a widely used circuit structure in LNA designs, is presented. The noise and the linearity improvement techniques for cascode structures are also developed and have been proven by computer simulating experiments. Theoretical analysis and simulation results showed that, for cascode structure LNAs, the first metallic oxide semiconductor field effect transistor (MOSFET) dominates the noise performance of the LNA, while the second MOSFET contributes more to the linearity. A conclusion is thus obtained that the first and second MOSFET of the LNA can be designed to optimize the noise performance and the linearity performance separately, without trade offs. The 1.9GHz Complementary Metal Oxide Semiconductor (CMOS) LNA simulation results are also given as an application of the developed theory.展开更多
文摘Novel schemes for a charge sensitive amplifier （CSA） and a CR-（RC）, semi-Gaussian shaper in a fully integrated CMOS readout circuit for particle detectors are presented. The CSA is designed with poly-resistors as feedback components to reduce noise. Compared with conventional CSA, the input referred equivalent noise charge（ENC） is simulated to be reduced from 5036e to 2381e with a large detector capacitance of 150pF at the cost of 0.5V output swing loss. The CR-（RC）,semi-Gaussian shaper uses MOS transistors in the triode region in series with poly-resistors to compensate process variation without much linearity reduction.
文摘A systematic approach is used to analyze the noise in CMOS low noise amplifier(LNA),including channel noise and induced gate noise in MOS devices.A new analytical formula for noise figure is proposed.Based on this formula,the impacts of distributed gate resistance and intrinsic channel resistance on noise performance are discussed.Two kinds of noise optimization approaches are performed and applied to the design of a 5 2GHz CMOS LNA.
基金supportedin part by Natural Science Foundation under grant No.91338108,91438206Co-innovation Laboratory of Aerospace Broadband Network Technology
文摘For digital channelized frequency division multiple access based satellite communication(SATCOM) systems,it is a challenging but critical issue to improve the transponder power and spectrum efficiency simultaneously under limited and non-linear high-power amplifier conditions.In this paper,different from the traditional link supportability designs aiming at minimizing the total transponder output power,a maximal sum Shannon capacity optimization objective is firstly raised subject to link supportability constraints.Furthermore,an efficient multilevel optimization(MO) algorithm is proposed to solve the considered optimization problem in the case of single link for each terminal.Moreover,in the case of multiple links for one terminal,an improved MO algorithm involving Golden section and discrete gradient searching procedures is proposed to optimize power allocation over all links.Finally,several numerical results are provided to demonstrate the effectiveness of our proposals.Comparison results show that,by the MO algorithm,not only all links' supportability can be guaranteed but also a larger sum capacity can be achieved with lower complexity.
文摘Noise and linearity performances are critical characteristics for radio frequency integrated circuits (RFICs), especially for low noise amplifiers (LNAs). In this paper, a detailed analysis of noise and linearity for the cascode architecture, a widely used circuit structure in LNA designs, is presented. The noise and the linearity improvement techniques for cascode structures are also developed and have been proven by computer simulating experiments. Theoretical analysis and simulation results showed that, for cascode structure LNAs, the first metallic oxide semiconductor field effect transistor (MOSFET) dominates the noise performance of the LNA, while the second MOSFET contributes more to the linearity. A conclusion is thus obtained that the first and second MOSFET of the LNA can be designed to optimize the noise performance and the linearity performance separately, without trade offs. The 1.9GHz Complementary Metal Oxide Semiconductor (CMOS) LNA simulation results are also given as an application of the developed theory.
