This paper presents a design method of ByPassing Unit(BPU) in 32-bit Digital Signal Processor(DSP)-MD32. MD32 is realized in 0,18μm technology, 1.8V and 200 MHz working clock. It focuses on the Reduced Instruction Se...This paper presents a design method of ByPassing Unit(BPU) in 32-bit Digital Signal Processor(DSP)-MD32. MD32 is realized in 0,18μm technology, 1.8V and 200 MHz working clock. It focuses on the Reduced Instruction Set Computer(RISC) architecture and DSP computation capability thoroughly, extends DSP with various addressing modes in a customized DSP pipeline stage architecture. The paper also discusses the architecture and circuit design of bypassing logic to fit MD32 architecture. The parallel execution of BPU with instruction decode in architecture level is applied to reduce time delay. The optimization of circuit that serial select with priority is analyzed in detail, and the result shows that about half of time delay is reduced after this optimization. Examples show that BPU is useful for improving the DSP's performance.The forwarding logic in MD32 realizes 8 data channels feedback and meets the working clock limit.展开更多
Human body communication is proposed as a promising body proximal comanunication tech- nology for body sensor networks. To achieve low power and slmll volume ill the sensor nodes, a Ra-dio Frequency (RF) application...Human body communication is proposed as a promising body proximal comanunication tech- nology for body sensor networks. To achieve low power and slmll volume ill the sensor nodes, a Ra-dio Frequency (RF) application-specific integrated circuit transceiver tbr Human Body Commnunication (HBC) is presented and the characteristics of HBC are investigated. A high data rate On-Off Keying (OOK)/Frequency-Shift Keying (FSK) modulation protocol and an OOK/FSK delrodulator circuit are introduced in this paper, with a data-rate-to-carrier-frequency ratio up to 70%. A low noise amplifier is proposed to handle the dynamic range problem and improve the sensitivity of the receiver path. In addi-tion, a low power autonmatic-gain-control system is realized using a novel architecture, thereby render-ing the peak detector circuit and loop filter unneces-sary. Finally, the complete chip is fabricated. Simula-tion results suggest receiver sensitivity to be-75 dBm. The transceiver shows an overall power con-smxption of 32 mW when data rate is 5 Mbps, de-livering a P1dB output power of - 30 dBm.展开更多
Low Voltage Differential Signaling (LVDS) has become a popular choice for high-speed serial links to conquer the bandwidth bottleneck of intra-chip data transmission. This paper presents the design and the implementat...Low Voltage Differential Signaling (LVDS) has become a popular choice for high-speed serial links to conquer the bandwidth bottleneck of intra-chip data transmission. This paper presents the design and the implementation of LVDS Input/Output (I/O) interface circuits in a standard 0.18 μm CMOS technology using thick gate oxide devices (3.3 V), fully compatible with LVDS standard. In the proposed transmitter, a novel Common-Mode FeedBack (CMFB)circuit is utilized to keep the common-mode output voltage stable over Process, supply Voltage and Temperature (PVT) variations. Because there are no area greedy resistors in the CMFB circuitry, the disadvantage of large die area in existing transmitter structures is avoided. To obtain sufficient gain, the receiver consists of three am- plifying stages: a voltage amplifying stage, a transconductance amplifying stage, and a transimpedance amplifying stage. And to exclude inner nodes with high RC time constant, shunt-shunt negative feedback is introduced in the receiver. A novel active inductor shunt peaking structure is used in the receiver to fulfill the stringent requirements of high speed and wide Common-Mode Input Region (CMIR) without voltage gain, power dissipation and silicon area penalty. Simulation results show that data rates of 2 Gbps and 2.5 Gbps are achieved for the transmitter and receiver with power con- sumption of 13.2 mW and 8.3 mW respectively.展开更多
Simultaneous dimming controlling and data transmission are usually required in a white LED based indoor visible light communication system.However,the diming controlling of LED normally interferes the data transmissio...Simultaneous dimming controlling and data transmission are usually required in a white LED based indoor visible light communication system.However,the diming controlling of LED normally interferes the data transmission due to the modulation nonlinearity of LED.In order to solve this problem,a scheme by separating the LEDs for the functions of dimming control and data transmission respectively is proposed in this paper.In the scheme,the LEDs used for dimming control function are driven by a dc amplified circuit,and the LEDs for data transmission are driven by a digital modulation circuit respectively.In this way,the modulation distortion to the data signal caused by the modulation nonlinearity can be avoided even if the dimming is at high level dc driven current.The proof-of-concept experiment of a 2.5Mbit/s visible light communication system demonstrates that the dimming controlling and data transmission can be realized simultaneously in a simple way,and the data transmission is not affected by the dimming controlling function.Compared to previous methods,the scheme in this paper is simpler and cost effective,and makes sense when high rate data is transmitted in a visible light communication system.展开更多
In this article, a transmission line is represented by a cascade of n circuits using a single phase. It is analyzed what is the reasonable number of n circuits and the number of blocks composed by parallel resistor an...In this article, a transmission line is represented by a cascade of n circuits using a single phase. It is analyzed what is the reasonable number of n circuits and the number of blocks composed by parallel resistor and inductor in parallel for reduction of numerical oscillations. It is simulated the numerical routine with and without the effectof frequency in the longitudinal parameters. Initially, it is used to state variables and 7t circuits representing the transmission line composing a linear system which is solved by numerical routines based on the trapezoidal rule. The effect of frequency on the line is synthesized by resistors and inductors in parallel and this representation is analyzed in details. It is described as transmission lines and the frequency influence in these lines through the state variables.展开更多
On the basis of analysis on the temperature monitoring methods for high voltage devices, a new type of fiber optic sensor structure with reference channel is given. And the operation principle of fiber optic sensor is...On the basis of analysis on the temperature monitoring methods for high voltage devices, a new type of fiber optic sensor structure with reference channel is given. And the operation principle of fiber optic sensor is analysed at large based on the absorption of semiconductor chip. The mathematical model of both devices and the whole system are also given. It is proved by the experiment that this mathematical model is reliable.展开更多
Digital TV (DTV) video signal transmission over ATM network is emphasized on.Some important problems are introduced about TV video signals asynchronous transfer to network application client, and the idea of video tra...Digital TV (DTV) video signal transmission over ATM network is emphasized on.Some important problems are introduced about TV video signals asynchronous transfer to network application client, and the idea of video transfer design is discussed. The contents mainly include the DTV video streams asynchronous transfer topology, compressed coding adopted ATM network, asynchronous transfer efficiency and some problems of DTV video transmission in ATM network .展开更多
基金Supported by the National High Technology Research & Development Program of China (863 Program) (2002AA1Z1140).
文摘This paper presents a design method of ByPassing Unit(BPU) in 32-bit Digital Signal Processor(DSP)-MD32. MD32 is realized in 0,18μm technology, 1.8V and 200 MHz working clock. It focuses on the Reduced Instruction Set Computer(RISC) architecture and DSP computation capability thoroughly, extends DSP with various addressing modes in a customized DSP pipeline stage architecture. The paper also discusses the architecture and circuit design of bypassing logic to fit MD32 architecture. The parallel execution of BPU with instruction decode in architecture level is applied to reduce time delay. The optimization of circuit that serial select with priority is analyzed in detail, and the result shows that about half of time delay is reduced after this optimization. Examples show that BPU is useful for improving the DSP's performance.The forwarding logic in MD32 realizes 8 data channels feedback and meets the working clock limit.
基金This study was supported partially by the Projects of National Natural Science Foundation of China under Crants No. 60932001, No.61072031 the National 863 Program of China un-der Crant No. 2012AA02A604+3 种基金 the National 973 Program of China under Cwant No. 2010CB732606 the Next Generation Communication Technology Major Project of National S&T un-der Crant No. 2013ZX03005013 the "One-hundred Talent" and the "Low-cost Healthcare" Programs of Chinese Academy of Sciences and the Guangdong Innovation Research Team Funds for Low-cost Healthcare and Irrage-Guided Therapy.
文摘Human body communication is proposed as a promising body proximal comanunication tech- nology for body sensor networks. To achieve low power and slmll volume ill the sensor nodes, a Ra-dio Frequency (RF) application-specific integrated circuit transceiver tbr Human Body Commnunication (HBC) is presented and the characteristics of HBC are investigated. A high data rate On-Off Keying (OOK)/Frequency-Shift Keying (FSK) modulation protocol and an OOK/FSK delrodulator circuit are introduced in this paper, with a data-rate-to-carrier-frequency ratio up to 70%. A low noise amplifier is proposed to handle the dynamic range problem and improve the sensitivity of the receiver path. In addi-tion, a low power autonmatic-gain-control system is realized using a novel architecture, thereby render-ing the peak detector circuit and loop filter unneces-sary. Finally, the complete chip is fabricated. Simula-tion results suggest receiver sensitivity to be-75 dBm. The transceiver shows an overall power con-smxption of 32 mW when data rate is 5 Mbps, de-livering a P1dB output power of - 30 dBm.
文摘Low Voltage Differential Signaling (LVDS) has become a popular choice for high-speed serial links to conquer the bandwidth bottleneck of intra-chip data transmission. This paper presents the design and the implementation of LVDS Input/Output (I/O) interface circuits in a standard 0.18 μm CMOS technology using thick gate oxide devices (3.3 V), fully compatible with LVDS standard. In the proposed transmitter, a novel Common-Mode FeedBack (CMFB)circuit is utilized to keep the common-mode output voltage stable over Process, supply Voltage and Temperature (PVT) variations. Because there are no area greedy resistors in the CMFB circuitry, the disadvantage of large die area in existing transmitter structures is avoided. To obtain sufficient gain, the receiver consists of three am- plifying stages: a voltage amplifying stage, a transconductance amplifying stage, and a transimpedance amplifying stage. And to exclude inner nodes with high RC time constant, shunt-shunt negative feedback is introduced in the receiver. A novel active inductor shunt peaking structure is used in the receiver to fulfill the stringent requirements of high speed and wide Common-Mode Input Region (CMIR) without voltage gain, power dissipation and silicon area penalty. Simulation results show that data rates of 2 Gbps and 2.5 Gbps are achieved for the transmitter and receiver with power con- sumption of 13.2 mW and 8.3 mW respectively.
基金financially supported by National Natural Science Foundation of China(No.61475094)National 973 Program of China(No.2013CB329202)
文摘Simultaneous dimming controlling and data transmission are usually required in a white LED based indoor visible light communication system.However,the diming controlling of LED normally interferes the data transmission due to the modulation nonlinearity of LED.In order to solve this problem,a scheme by separating the LEDs for the functions of dimming control and data transmission respectively is proposed in this paper.In the scheme,the LEDs used for dimming control function are driven by a dc amplified circuit,and the LEDs for data transmission are driven by a digital modulation circuit respectively.In this way,the modulation distortion to the data signal caused by the modulation nonlinearity can be avoided even if the dimming is at high level dc driven current.The proof-of-concept experiment of a 2.5Mbit/s visible light communication system demonstrates that the dimming controlling and data transmission can be realized simultaneously in a simple way,and the data transmission is not affected by the dimming controlling function.Compared to previous methods,the scheme in this paper is simpler and cost effective,and makes sense when high rate data is transmitted in a visible light communication system.
文摘In this article, a transmission line is represented by a cascade of n circuits using a single phase. It is analyzed what is the reasonable number of n circuits and the number of blocks composed by parallel resistor and inductor in parallel for reduction of numerical oscillations. It is simulated the numerical routine with and without the effectof frequency in the longitudinal parameters. Initially, it is used to state variables and 7t circuits representing the transmission line composing a linear system which is solved by numerical routines based on the trapezoidal rule. The effect of frequency on the line is synthesized by resistors and inductors in parallel and this representation is analyzed in details. It is described as transmission lines and the frequency influence in these lines through the state variables.
文摘On the basis of analysis on the temperature monitoring methods for high voltage devices, a new type of fiber optic sensor structure with reference channel is given. And the operation principle of fiber optic sensor is analysed at large based on the absorption of semiconductor chip. The mathematical model of both devices and the whole system are also given. It is proved by the experiment that this mathematical model is reliable.
文摘Digital TV (DTV) video signal transmission over ATM network is emphasized on.Some important problems are introduced about TV video signals asynchronous transfer to network application client, and the idea of video transfer design is discussed. The contents mainly include the DTV video streams asynchronous transfer topology, compressed coding adopted ATM network, asynchronous transfer efficiency and some problems of DTV video transmission in ATM network .