12导D/AC反馈型心电信号放大器的研究

本文提出了一种新型的多通道前置放大器，并采用D/AC补偿极化电压的方法，实现了高性能的直流12导心电放大器。本文详细地讨论了该放大器的设计，并给出了在有工频干扰的情况下放大器自动调零的方法。采用本文给出的放大器，可以实现低成本、免调试和高性能的多通道生物电的采集。

Design of Pipelined ADC Using Op Amp Sharing Technique

This paper presents a 10-bit 20 MS/s pipelined Analog-to- Digital Converter（ADC） using op amp sharing approach and removing Sample and Hold Amplifier（SHA） or SHA-less technique to reach the goal of low-power constanpfion. This design was fabricated in TSMC 0.18 wn 1P6M technology. Measurement results show at supply voltage of 1.8 V, a SFDR of 42.46 dB, a SNDR of 39.45 dB, an ENOB of 6.26, and a THDof41.82 dB are at 1 MHz sinusoidal sig- nal input. In addition, the DNL and INL are 1.4 LSB and 3.23 LSB respectively. The power onstmaption is 28.8 mW. The core area is 0.595 mm2 and the chip area including pads is 1.468 mm2.

High Speed Column-Parallel CDS/ADC Circuit with Nonlinearity Compensation for CMOS Image Sensors

A high speed column-parallel CDS/ADC circuit with nonlinearity compensation is proposed in this paper.The correlated double sampling (CDS) and analog-to-digital converter (ADC) functions are integrated in a threephase column-parallel circuit based on two floating gate inverters and switched-capacitor network.The conversion rate of traditional single-slope ADC is speeded up by dividing quantization to coarse step and fine step.A storage capacitor is used to store the result of coarse step and locate the section of ramp signal of fine step,which can reduce the clock step from 2 n to 2 (n/2+1).The floating gate inverters are implemented to reduce the power consumption.Its induced nonlinear offset is cancelled by introducing a compensation module to the input of inverter,which can equalize the coupling path in three phases of the proposed circuit.This circuit is designed and simulated for CMOS image sensor with 640×480 pixel array using Chartered 0.18μm process.Simulation results indicate that the resolution can reach 10-bit and the maximum frame rate can reach 200 frames/s with a main clock of 10MHz.The power consumption of this circuit is less than 36.5μW with a 3.3V power supply.The proposed CDS/ADC circuit is suitable for high resolution and high speed image sensors.

Feedback Filtering for Digital Control Applications

Thanks to the progress in semiconductor technologies, today microcontrollers offer huge computational power. That allows using advanced control algorithms with a built-in intelligence with a sufficient speed, for many demanding applications. These capabilities make the embedded control ideal for using at complex plants and for obtaining the highest performance in a wide area of operations. However, control performance also strongly depends on the feedback. A short latency and a high precision of embedded analog peripherals allow building fast and accurate control loops. The paper proposes an easy design method of high performance analog to digital converter filtering path, optimized for control applications.

The Practical Design Aspects of Anti-aliasing Filters for the Multirate Analog-to-digital Processing in Microcontroller Embedded System

Due to the widespread computer technology, it is difficult to imagine a research or a control of any physical object without using a powerful hardware and software applications. To use digital technologies we need to collect data of a real world in digital system by the analog-to-digital converters. Taking into account the relative high computational capabilities of modern microcontrollers the article proposes a multirate processing system. The paper presents practical design aspects of the analog and digital anti-aliasing filter fbr the measurement path. having regarded the real possibilities and limitations of today＇s filters and analog-to-digital embedded converters.

High-resolution data acquisition technique in broadband seismic observation systems

The dynamic range of the currently most widely used 24-bit seismic data acquisition devices is 10–20 d B lower than that of broadband seismometers, and this can affect the completeness of seismic waveform recordings under certain conditions. However, this problem is not easy to solve because of the lack of analog to digital converter(ADC) chips with more than 24 bits in the market. In this paper, we propose a method in which an adder, an integrator, a digital to analog converter chip, a field-programmable gate array, and an existing low-resolution ADC chip are used to build a third-order 16-bit oversampling delta-sigma modulator. This modulator is equipped with a digital decimation filter, thus facilitating higher resolution and larger dynamic range seismic data acquisition. Experimental results show that, within the 0.1–40 Hz frequency range, the circuit board's dynamic range reaches 158.2 d B, its resolution reaches 25.99 bits, and its linearity error is below 2.5 ppm, which is better than what is achieved by the commercial 24-bit ADC chips ADS1281 and CS5371. This demonstrates that the proposed method may alleviate or even completely resolve the amplitude-limitation problem that so commonly occurs with broadband observation instruments during strong earthquakes.