Cascaded multilevel converters built with integrated modules have many advantages such as increased power density,flexible distributed control,multi-functionality,increased reliability and short design cycles.However,...Cascaded multilevel converters built with integrated modules have many advantages such as increased power density,flexible distributed control,multi-functionality,increased reliability and short design cycles.However,the system performance will be affected due to the synchronization errors among each integrated modules.This paper analyzes the impact of the three kinds of synchronization errors on the whole system performance,as well as detailed synchronization implementation.Some valuable conclusions are derived from the theoretical analysis,simulations and experimental results.展开更多
Triple-threshold CMOS technique provides the transistors that have low-, normal-, and high-threshold voltage. This paper describes a low-power carry look-ahead adder with triple-threshold CMOS technique. While the low...Triple-threshold CMOS technique provides the transistors that have low-, normal-, and high-threshold voltage. This paper describes a low-power carry look-ahead adder with triple-threshold CMOS technique. While the low-threshold voltage transistors are used to reduce the propagation delay time in the critical path, the high-threshold voltage transistors are used to reduce the power consumption in the shortest path. Comparing with the conventional CMOS circuit, the circuit is achieved to reduce the power consumption by 14.71% and the power-delay-product by 16.11%. This circuit is designed with Samsung 0.35 um CMOS process. The validity and effectiveness are verified through the HSPICE simulation.展开更多
基金Project supported by the National Natural Science Foundation of China (No. 50277035)the Natural Science Foundation of Zheji-ang Province (No. Z104441),China
文摘Cascaded multilevel converters built with integrated modules have many advantages such as increased power density,flexible distributed control,multi-functionality,increased reliability and short design cycles.However,the system performance will be affected due to the synchronization errors among each integrated modules.This paper analyzes the impact of the three kinds of synchronization errors on the whole system performance,as well as detailed synchronization implementation.Some valuable conclusions are derived from the theoretical analysis,simulations and experimental results.
文摘Triple-threshold CMOS technique provides the transistors that have low-, normal-, and high-threshold voltage. This paper describes a low-power carry look-ahead adder with triple-threshold CMOS technique. While the low-threshold voltage transistors are used to reduce the propagation delay time in the critical path, the high-threshold voltage transistors are used to reduce the power consumption in the shortest path. Comparing with the conventional CMOS circuit, the circuit is achieved to reduce the power consumption by 14.71% and the power-delay-product by 16.11%. This circuit is designed with Samsung 0.35 um CMOS process. The validity and effectiveness are verified through the HSPICE simulation.
