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一种数据时钟恢复电路的研究与设计
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作者 周玮 周叶 杨品一 《微电子学》 CAS CSCD 北大核心 2011年第6期860-864,共5页
提出了一种支持双数据率的数据时钟恢复电路,对电路中的鉴相器、环路滤波器、压控振荡器等进行了详细的分析研究和设计。基于0.18μm CMOS工艺,在电源电压1.8V下对电路进行仿真。仿真结果显示,电路在2.7Gb/s和1.62Gb/s随机流下的抖动峰... 提出了一种支持双数据率的数据时钟恢复电路,对电路中的鉴相器、环路滤波器、压控振荡器等进行了详细的分析研究和设计。基于0.18μm CMOS工艺,在电源电压1.8V下对电路进行仿真。仿真结果显示,电路在2.7Gb/s和1.62Gb/s随机流下的抖动峰峰值分别为14ps和12ps,功耗为80mW。测试结果显示,时钟恢复电路在2.7Gb/s和1.62Gb/s随机流下的抖动峰峰值分别为38ps和27ps。 展开更多
关键词 锁相环 数据时钟恢复电路 抖动 相位噪声 压控振荡器
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2.5Gb/s Monolithic IC of Clock Recovery,Data Decision,and 1∶4 Demultiplexer 被引量:2
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作者 陈莹梅 王志功 +1 位作者 熊明珍 章丽 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2005年第8期1532-1536,共5页
A high integrated monolithic IC, with functions of clock recovery, data decision, and 1 : 4 demultiplexer,is implemented in 0.25μm CMOS process for 2.5Gb/s fiber-optic communications. The recovered and frequency div... A high integrated monolithic IC, with functions of clock recovery, data decision, and 1 : 4 demultiplexer,is implemented in 0.25μm CMOS process for 2.5Gb/s fiber-optic communications. The recovered and frequency divided 625MHz clock has a phase noise of -106.26dBc/Hz at 100kHz offset in response to a 2.5Gb/s PRBS input data (2^31-1). The 2.5Gb/s PRBS data are demultiplexed to four 625Mb/s data. The 0.97mm× 0.97mm IC consumes 550mW under a single 3.3V power supply (not including output buffers). 展开更多
关键词 optical transmission systems clock recovery circuits data decision 1 4 demultiplexer charge pump phase-locked loops
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Modeling for Ethernet passive optical network receiver
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作者 张亮 王志功 +1 位作者 胡庆生 邓伟杰 《Journal of Southeast University(English Edition)》 EI CAS 2009年第4期439-444,共6页
A behavior model for the receiver of the Ethernet passive optical network(EPON) is presented. The model consists of a fiber, a photodetector, a transimpedance amplifier (TIA) followed by a limiting amplifier and a... A behavior model for the receiver of the Ethernet passive optical network(EPON) is presented. The model consists of a fiber, a photodetector, a transimpedance amplifier (TIA) followed by a limiting amplifier and a clock and data recovery' circuit (CDR). Each sub-model is constructed based on the architecture of a circuit. The noise and jitter in each block such as shot noise, thermal noise, deterministic and random jitter are also considered. The performance of the whole receiver can be evaluated by the simulation of the behavior model, which is faster than the ordinary circuit model and more accurate than the analytical model. The whole model is implemented with C ++ and simulated in Microsoft Visual C ++ 6. 0. Using the Monte Carlo method, the EPON receiver is simulated. The simulation results show a good agreement with experimental ones. 展开更多
关键词 Ethel'net passive optical network(EPON) behavior model noise JITTER clock and data recovery circuit(CDR)
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