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受控与涉及旁径的n维单形不等式
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作者 朱杏华 《宝鸡文理学院学报(自然科学版)》 CAS 2002年第2期105-108,122,共5页
应用受控理论与方法研究单形 ,给出了 n维单形中旁切超球半径 ,内切超球半径及高线长之间的若干受控关系 ,简捷地建立了 n维单形中涉及旁切超球半径的一系列新的几何不等式。
关键词 受控 旁径 单形 几何不等式
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对两个与旁径有关几何不等式的再探
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作者 丁遵标 《河北理科教学研究》 2014年第3期41-41,共1页
匡继昌教授在《常用不等式》一书中,收录了下面的两个几何不等式:
关键词 几何不等式 旁径 中学 数学教学 教学方法
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RADIOFREQUENCY CURRENT CATHETER ABLATION OF THE LEFT ATRIOVENTRICULAR ACCESSORY PATHWAYS WITH PAROXYSMAL SUPRAVENTRICULAR TACHYCARDIA 被引量:1
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作者 王静毅 郭继鸿 +5 位作者 吴益明 朱继红 王伟民 赵红 刘喜荣 MichaelA.Lee 《Chinese Medical Sciences Journal》 CAS CSCD 1994年第2期132-134,共3页
Seventy patients with left atrioventricular accessory pathways and paroxysmal supraventricular tachycardia(PSVT) underwent radiofrequency catheter ablation(RFCA). The success rate was 94. 3%. Among these patients,26 h... Seventy patients with left atrioventricular accessory pathways and paroxysmal supraventricular tachycardia(PSVT) underwent radiofrequency catheter ablation(RFCA). The success rate was 94. 3%. Among these patients,26 had manifest preexcitation syndrome, and 44 had concealed preexcitation. Eighteen patients with concealed preexcitation underwent coronary sinus (CS) pacing, and delta wave appeared in 15. The keys to successful RFCA were correct positioning of the radiofrequency(RF) catheter tip, A/V amplitude ratio, AV interval (in sinus rhythm) and VA interval(during SVT or ventricular pacing). After 1~14 months of follow-up. two patients had supraventricular tachycardia(SVT) recurrence. 展开更多
关键词 Wolff-Parkinson-White syndrome catheter ablation supraventricular tachycardia
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DATA BYPASSING ARCHITECTURE AND CIRCUIT DESIGN FOR 32-BIT DIGITAL SIGNAL PROCESSOR 被引量:2
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作者 Chen Xiaoyi Yao Qingdong Liu Peng 《Journal of Electronics(China)》 2005年第6期640-649,共10页
This paper presents a design method of ByPassing Unit(BPU) in 32-bit Digital Signal Processor(DSP)-MD32. MD32 is realized in 0,18μm technology, 1.8V and 200 MHz working clock. It focuses on the Reduced Instruction Se... This paper presents a design method of ByPassing Unit(BPU) in 32-bit Digital Signal Processor(DSP)-MD32. MD32 is realized in 0,18μm technology, 1.8V and 200 MHz working clock. It focuses on the Reduced Instruction Set Computer(RISC) architecture and DSP computation capability thoroughly, extends DSP with various addressing modes in a customized DSP pipeline stage architecture. The paper also discusses the architecture and circuit design of bypassing logic to fit MD32 architecture. The parallel execution of BPU with instruction decode in architecture level is applied to reduce time delay. The optimization of circuit that serial select with priority is analyzed in detail, and the result shows that about half of time delay is reduced after this optimization. Examples show that BPU is useful for improving the DSP's performance.The forwarding logic in MD32 realizes 8 data channels feedback and meets the working clock limit. 展开更多
关键词 Digital Signal Processor(DSP) Customized pipeline FORWARDING Bypassing MD32
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