The Paper introduces an IF software radio receiver development Platform based on high-speed monolithic A/D Converter AD6640, Progranunable Digital Down-converter AD6620 and high-speed DSP chip TMSC320C6701. The implem...The Paper introduces an IF software radio receiver development Platform based on high-speed monolithic A/D Converter AD6640, Progranunable Digital Down-converter AD6620 and high-speed DSP chip TMSC320C6701. The implementation method is described as well as AD6620 parameter setting analysis. It also presents a flow chart of the on-line programming with the help of PC. The algorithm for demodulation AM signal is discussed.展开更多
High efficiency audio compression is the basic technology in audio involved multimedia communications. Downmixing and parametric coding is efficient coding scheme with wide applications in some up-to-date audio codecs...High efficiency audio compression is the basic technology in audio involved multimedia communications. Downmixing and parametric coding is efficient coding scheme with wide applications in some up-to-date audio codecs such as Parametric Stereo (PS) in EAAC+ and MPEG-Surround. Principle Component Analysis (PCA) stereo coding followed this idea to map two channels to one channel with maximum energy and parameterize the secondary channel. This paper investigates the conventional PCA method performance under general stereo model with multiple sound sources and different directions, and then proposes a Polar Coordinate based PCA (PC-PCA) stereo coding method. It has been proved that when multiple sound sources exist with different directions, PC-PCA is better than the conventional PCA method when Mean to Standard deviation Ratio (MSR) is large. A stereo codec based on PC-PCA is proposed to validate the performance improvement of proposed method. Objective and subjective tests show the proposed method achieves a comparative quality and saves 50% parameter bit rate comparing with conventional PCA method, and obtains a 4-8 MUSHRA scores improvement comparing with state-of-the-art stereo codec at the same parameter bit rate.展开更多
Noise and linearity performances are critical characteristics for radio frequency integrated circuits (RFICs), especially for low noise amplifiers (LNAs). In this paper, a detailed analysis of noise and linearity for ...Noise and linearity performances are critical characteristics for radio frequency integrated circuits (RFICs), especially for low noise amplifiers (LNAs). In this paper, a detailed analysis of noise and linearity for the cascode architecture, a widely used circuit structure in LNA designs, is presented. The noise and the linearity improvement techniques for cascode structures are also developed and have been proven by computer simulating experiments. Theoretical analysis and simulation results showed that, for cascode structure LNAs, the first metallic oxide semiconductor field effect transistor (MOSFET) dominates the noise performance of the LNA, while the second MOSFET contributes more to the linearity. A conclusion is thus obtained that the first and second MOSFET of the LNA can be designed to optimize the noise performance and the linearity performance separately, without trade offs. The 1.9GHz Complementary Metal Oxide Semiconductor (CMOS) LNA simulation results are also given as an application of the developed theory.展开更多
文摘The Paper introduces an IF software radio receiver development Platform based on high-speed monolithic A/D Converter AD6640, Progranunable Digital Down-converter AD6620 and high-speed DSP chip TMSC320C6701. The implementation method is described as well as AD6620 parameter setting analysis. It also presents a flow chart of the on-line programming with the help of PC. The algorithm for demodulation AM signal is discussed.
基金supported by National Natural Science Foundation of China under Grants No. 61231015, No. 61102127 No. 61201340, No. 61201169Major National Science and Technology Special Projects under Grant No. 2010ZX03004-003-03+2 种基金Natural Science Foundation of Hubei Province under Grant No. 2011CDB451Wuhan ChenGuang Science and Technology Plan under Grant No. 201150431104the Fundamental Research Funds for the Central Universities
文摘High efficiency audio compression is the basic technology in audio involved multimedia communications. Downmixing and parametric coding is efficient coding scheme with wide applications in some up-to-date audio codecs such as Parametric Stereo (PS) in EAAC+ and MPEG-Surround. Principle Component Analysis (PCA) stereo coding followed this idea to map two channels to one channel with maximum energy and parameterize the secondary channel. This paper investigates the conventional PCA method performance under general stereo model with multiple sound sources and different directions, and then proposes a Polar Coordinate based PCA (PC-PCA) stereo coding method. It has been proved that when multiple sound sources exist with different directions, PC-PCA is better than the conventional PCA method when Mean to Standard deviation Ratio (MSR) is large. A stereo codec based on PC-PCA is proposed to validate the performance improvement of proposed method. Objective and subjective tests show the proposed method achieves a comparative quality and saves 50% parameter bit rate comparing with conventional PCA method, and obtains a 4-8 MUSHRA scores improvement comparing with state-of-the-art stereo codec at the same parameter bit rate.
文摘Noise and linearity performances are critical characteristics for radio frequency integrated circuits (RFICs), especially for low noise amplifiers (LNAs). In this paper, a detailed analysis of noise and linearity for the cascode architecture, a widely used circuit structure in LNA designs, is presented. The noise and the linearity improvement techniques for cascode structures are also developed and have been proven by computer simulating experiments. Theoretical analysis and simulation results showed that, for cascode structure LNAs, the first metallic oxide semiconductor field effect transistor (MOSFET) dominates the noise performance of the LNA, while the second MOSFET contributes more to the linearity. A conclusion is thus obtained that the first and second MOSFET of the LNA can be designed to optimize the noise performance and the linearity performance separately, without trade offs. The 1.9GHz Complementary Metal Oxide Semiconductor (CMOS) LNA simulation results are also given as an application of the developed theory.
