[Objective] The aim of the research was to study the effect of the ice bath time after heat shock and the incubation time on the transformation efficacy,and to establish a simple and quick transformation method.[Metho...[Objective] The aim of the research was to study the effect of the ice bath time after heat shock and the incubation time on the transformation efficacy,and to establish a simple and quick transformation method.[Method]Competent cells were prepared with two buffer solutions;with the ice bath time after heat shock and the recovery time as the variables,the relationship between these two factors and transformation efficacy was studied.[Result]The transformation efficacy was the best when the ice bath time was 2 min and the recovery time was 30 or 40 min;when the ice bath time and the recovery time was 0 min,a certain amount of transformants still could be obtained.[Conclusion]The ice bath time after heat shock and the recovery time had certain impact on transformation efficacy,but they were not the decisive factors.Therefore,in the general transformation experiment,these two steps could be omitted.展开更多
The interleaving/multiplexing technique was used to realize a 200?MHz real time data acquisition system. Two 100?MHz ADC modules worked parallelly and every ADC plays out data in ping pang fashion. The design improv...The interleaving/multiplexing technique was used to realize a 200?MHz real time data acquisition system. Two 100?MHz ADC modules worked parallelly and every ADC plays out data in ping pang fashion. The design improved the system conversion rata to 200?MHz and reduced the speed of data transporting and storing to 50?MHz. The high speed HDPLD and ECL logic parts were used to control system timing and the memory address. The multi layer print board and the shield were used to decrease interference produced by the high speed circuit. The system timing was designed carefully. The interleaving/multiplexing technique could improve the system conversion rata greatly while reducing the speed of external digital interfaces greatly. The design resolved the difficulties in high speed system effectively. The experiment proved the data acquisition system is stable and accurate.展开更多
The design of a 2. 488 Gbit/s clock and data recovery (CDR) If for synchronous digital hierarchy (SDH) STM-16 receiver is described. Based on the injected phase-locked loop (IPLL) and D-flip flop architectures, ...The design of a 2. 488 Gbit/s clock and data recovery (CDR) If for synchronous digital hierarchy (SDH) STM-16 receiver is described. Based on the injected phase-locked loop (IPLL) and D-flip flop architectures, the CDR IC was implemented in a standard 0. 35 μan complementary metal-oxide-semiconductor (CMOS) technology. With 2^31 -1 pseudorandom bit sequences (PRBS) input, the sensitivity of data recovery circuit is less than 20 mV with 10^-12 bit error rate (BER). The recovered clock shows a root mean square (rms) jitter of 2. 8 ps and a phase noise of - 110 dBc/Hz at 100 kHz offset. The capture range of the circuit is larger than 40 MHz. With a 5 V supply, the circuit consumes 680 mW and the chip area is 1.49 mm × 1 mm.展开更多
基金Supported by Foundation for Returned Scholars of Hebei Province(2010)Research Fund for the Doctoral Program of Hebei Normal University(L2009B13)~~
文摘[Objective] The aim of the research was to study the effect of the ice bath time after heat shock and the incubation time on the transformation efficacy,and to establish a simple and quick transformation method.[Method]Competent cells were prepared with two buffer solutions;with the ice bath time after heat shock and the recovery time as the variables,the relationship between these two factors and transformation efficacy was studied.[Result]The transformation efficacy was the best when the ice bath time was 2 min and the recovery time was 30 or 40 min;when the ice bath time and the recovery time was 0 min,a certain amount of transformants still could be obtained.[Conclusion]The ice bath time after heat shock and the recovery time had certain impact on transformation efficacy,but they were not the decisive factors.Therefore,in the general transformation experiment,these two steps could be omitted.
文摘The interleaving/multiplexing technique was used to realize a 200?MHz real time data acquisition system. Two 100?MHz ADC modules worked parallelly and every ADC plays out data in ping pang fashion. The design improved the system conversion rata to 200?MHz and reduced the speed of data transporting and storing to 50?MHz. The high speed HDPLD and ECL logic parts were used to control system timing and the memory address. The multi layer print board and the shield were used to decrease interference produced by the high speed circuit. The system timing was designed carefully. The interleaving/multiplexing technique could improve the system conversion rata greatly while reducing the speed of external digital interfaces greatly. The design resolved the difficulties in high speed system effectively. The experiment proved the data acquisition system is stable and accurate.
文摘The design of a 2. 488 Gbit/s clock and data recovery (CDR) If for synchronous digital hierarchy (SDH) STM-16 receiver is described. Based on the injected phase-locked loop (IPLL) and D-flip flop architectures, the CDR IC was implemented in a standard 0. 35 μan complementary metal-oxide-semiconductor (CMOS) technology. With 2^31 -1 pseudorandom bit sequences (PRBS) input, the sensitivity of data recovery circuit is less than 20 mV with 10^-12 bit error rate (BER). The recovered clock shows a root mean square (rms) jitter of 2. 8 ps and a phase noise of - 110 dBc/Hz at 100 kHz offset. The capture range of the circuit is larger than 40 MHz. With a 5 V supply, the circuit consumes 680 mW and the chip area is 1.49 mm × 1 mm.