Leakage power is the dominant source of power dissipation for Sub-100 nm VLSI （very large scale integration） circuits. Various techniques were proposed to reduce the leakage power at nano-scale; one of these techniq...Leakage power is the dominant source of power dissipation for Sub-100 nm VLSI （very large scale integration） circuits. Various techniques were proposed to reduce the leakage power at nano-scale; one of these techniques is MTV （multi-threshold voltage） In this paper, the exact and optimal value of threshold voltage （Vth） for each transistor in any sequential circuit in the design is found, so that the value of the total leakage current in the design is at the minimum. This could be achieved by applying AI （artificial intelligence） search algorithm. The proposed algorithm is called LOAIS （leakage optimization using AI search）. LOAIS exploits the total slack time of each transistor＇s location and their contributions in the leakage current. It is introduced by AI heuristic search algorithms under 22 nm BSIM4 predictive technology model. The proposed approach saves around 80% of the sub-threshold leakage current without degrading the performance of the circuit.展开更多
文摘Leakage power is the dominant source of power dissipation for Sub-100 nm VLSI （very large scale integration） circuits. Various techniques were proposed to reduce the leakage power at nano-scale; one of these techniques is MTV （multi-threshold voltage） In this paper, the exact and optimal value of threshold voltage （Vth） for each transistor in any sequential circuit in the design is found, so that the value of the total leakage current in the design is at the minimum. This could be achieved by applying AI （artificial intelligence） search algorithm. The proposed algorithm is called LOAIS （leakage optimization using AI search）. LOAIS exploits the total slack time of each transistor＇s location and their contributions in the leakage current. It is introduced by AI heuristic search algorithms under 22 nm BSIM4 predictive technology model. The proposed approach saves around 80% of the sub-threshold leakage current without degrading the performance of the circuit.
