本系统主要对伪随机序列数据流中的位同步时钟提取和位同步时钟频率测量进行重点设计,采用ALTERA提供的Cyclone V 5CSEMA5F31C6芯片作为主控制器。该系统的创新点在于接收端在传统的数字锁相环(DPLL)的基础上还采用了一种等精度测频法...本系统主要对伪随机序列数据流中的位同步时钟提取和位同步时钟频率测量进行重点设计,采用ALTERA提供的Cyclone V 5CSEMA5F31C6芯片作为主控制器。该系统的创新点在于接收端在传统的数字锁相环(DPLL)的基础上还采用了一种等精度测频法来捕获位同步时钟的频率。通过多项测试,分析并记录数据,结果显示该系统的各项指标均能较好完成设计要求。展开更多
In this paper,a detailed analysis of a phase interpolator for clock recovery is presented. A mathematical model is setup for the phase interpolator and we perform a precise analysis using this model. The result shows ...In this paper,a detailed analysis of a phase interpolator for clock recovery is presented. A mathematical model is setup for the phase interpolator and we perform a precise analysis using this model. The result shows that the output amplitude and linearity of phase interpolator is primarily related to the difference between the two input phases. A new encoding pattern is given to solve this problem. Analysis in the circuit domain was also undertaken. The simulation results show that the relation between RC time-constant and time difference of input clocks affects the linearity of the phase interpolator. To alleviate this undesired effect, two adjustable-RC buffers are added at the input of the PI. Finally,a 90nm CMOS phase interpolator,which can work in the frequency from 1GHz to 5GHz,is proposed. The power dissipation of the phase interpolator is lmW with a 1.2V power supply. Experiment results show that the phase interpolator has a monotone output phase and good linearity.展开更多
In this paper, the design of a coarse-fine interpolation Time-to-Digital Converter (TDC) is implemented in an ALTERA’s Cyclone FPGA. The carry-select chain performs as the tapped delay line. The Logic Array Block (LA...In this paper, the design of a coarse-fine interpolation Time-to-Digital Converter (TDC) is implemented in an ALTERA’s Cyclone FPGA. The carry-select chain performs as the tapped delay line. The Logic Array Block (LAB) having a propagation delay of 165 ps in the chain is synthesized as delay cell. Coarse counters triggered by the global clock count the more significant bits of the time data. This clock is also fed through the delay line, and LABs create the copies. The replicas are latched by the tested event signal, and the less significant bits are encoded from the latched binary bits. Single-shot resolution of the TDC can be 60 ps. The worst Differential Nonlinearity (DNL) is about 0.2 Least Significant Bit (LSB, 165 ps in this TDC module), and the Integral Nonlinearity (INL) is 0.6 LSB. In comparison with other architectures using the synchronous global clock to sample the taps, this architecture consumed less electric power and logic cells, and is more stable.展开更多
This paper presents a source localization algorithm based on the source signal's time-difference-of-arrival(TDOA) for asynchronous wireless sensor network.To obtain synchronization among anchors,all anchors broadc...This paper presents a source localization algorithm based on the source signal's time-difference-of-arrival(TDOA) for asynchronous wireless sensor network.To obtain synchronization among anchors,all anchors broadcast signals periodically,the clock offsets and skews of anchor pairs can be estimated using broadcasting signal's time-of-arrivals(TOA) at anchors.A kalman filter is adopted to improve the accuracy of clock offsets and track the clock drifts due to random fluctuations.Once the source transmits signal,the TOAs at anchors are stamped respectively and source's TDOA error due to clock offset and skew of anchor pair can be mitigated by a compensation operation.Based on a Gaussian noise model,maximum likelihood estimation(MLE) for the source position is obtained.Performance issues are addressed by evaluating the Cramer-Rao lower bound and the selection of broadcasting period.The proposed algorithm is simple and effective,which has close performance with synchronous TDOA algorithm.展开更多
Based on the analyses for the characteristics of high precise GPS defor-mation monitor,according to the spatial relationship among the satellite, base point and monitoring point a new model and its corresponding algor...Based on the analyses for the characteristics of high precise GPS defor-mation monitor,according to the spatial relationship among the satellite, base point and monitoring point a new model and its corresponding algorithm were presented to solve the monitoring point deformation directly at single epoch. In this method the carrier phases is used as the basic observations, and the initial condition is precise baseline vectors obtained in the first period observations between the base point and monitoring point. This model is called the similar single difference model (SSDM). The main error sources effecting the accuracy of deformations were analyzed briefly, the single epoch algorithm of the receiver clock offset was advanced. The numerical results of test data show that the SSDM and the single epoch algorithm of receiver clock offset advanced are reliable and correct.展开更多
文摘本系统主要对伪随机序列数据流中的位同步时钟提取和位同步时钟频率测量进行重点设计,采用ALTERA提供的Cyclone V 5CSEMA5F31C6芯片作为主控制器。该系统的创新点在于接收端在传统的数字锁相环(DPLL)的基础上还采用了一种等精度测频法来捕获位同步时钟的频率。通过多项测试,分析并记录数据,结果显示该系统的各项指标均能较好完成设计要求。
文摘In this paper,a detailed analysis of a phase interpolator for clock recovery is presented. A mathematical model is setup for the phase interpolator and we perform a precise analysis using this model. The result shows that the output amplitude and linearity of phase interpolator is primarily related to the difference between the two input phases. A new encoding pattern is given to solve this problem. Analysis in the circuit domain was also undertaken. The simulation results show that the relation between RC time-constant and time difference of input clocks affects the linearity of the phase interpolator. To alleviate this undesired effect, two adjustable-RC buffers are added at the input of the PI. Finally,a 90nm CMOS phase interpolator,which can work in the frequency from 1GHz to 5GHz,is proposed. The power dissipation of the phase interpolator is lmW with a 1.2V power supply. Experiment results show that the phase interpolator has a monotone output phase and good linearity.
基金Supported by National Natural Science Foundation of China (No. 10405023)Knowledge Innovation Program of The Chinese Academy of Sciences (KJCX2-YW-N27)
文摘In this paper, the design of a coarse-fine interpolation Time-to-Digital Converter (TDC) is implemented in an ALTERA’s Cyclone FPGA. The carry-select chain performs as the tapped delay line. The Logic Array Block (LAB) having a propagation delay of 165 ps in the chain is synthesized as delay cell. Coarse counters triggered by the global clock count the more significant bits of the time data. This clock is also fed through the delay line, and LABs create the copies. The replicas are latched by the tested event signal, and the less significant bits are encoded from the latched binary bits. Single-shot resolution of the TDC can be 60 ps. The worst Differential Nonlinearity (DNL) is about 0.2 Least Significant Bit (LSB, 165 ps in this TDC module), and the Integral Nonlinearity (INL) is 0.6 LSB. In comparison with other architectures using the synchronous global clock to sample the taps, this architecture consumed less electric power and logic cells, and is more stable.
基金supported by the National Natural Science Foundation of China under Grant No.61571452 and No.61201331
文摘This paper presents a source localization algorithm based on the source signal's time-difference-of-arrival(TDOA) for asynchronous wireless sensor network.To obtain synchronization among anchors,all anchors broadcast signals periodically,the clock offsets and skews of anchor pairs can be estimated using broadcasting signal's time-of-arrivals(TOA) at anchors.A kalman filter is adopted to improve the accuracy of clock offsets and track the clock drifts due to random fluctuations.Once the source transmits signal,the TOAs at anchors are stamped respectively and source's TDOA error due to clock offset and skew of anchor pair can be mitigated by a compensation operation.Based on a Gaussian noise model,maximum likelihood estimation(MLE) for the source position is obtained.Performance issues are addressed by evaluating the Cramer-Rao lower bound and the selection of broadcasting period.The proposed algorithm is simple and effective,which has close performance with synchronous TDOA algorithm.
基金Doctor Foundation of Anhui University of Science and Technology.
文摘Based on the analyses for the characteristics of high precise GPS defor-mation monitor,according to the spatial relationship among the satellite, base point and monitoring point a new model and its corresponding algorithm were presented to solve the monitoring point deformation directly at single epoch. In this method the carrier phases is used as the basic observations, and the initial condition is precise baseline vectors obtained in the first period observations between the base point and monitoring point. This model is called the similar single difference model (SSDM). The main error sources effecting the accuracy of deformations were analyzed briefly, the single epoch algorithm of the receiver clock offset was advanced. The numerical results of test data show that the SSDM and the single epoch algorithm of receiver clock offset advanced are reliable and correct.
