5个不朽的法则

最先出现的摩尔定律又衍生出半导体工业的其他几个基本法则 Brian Halla,美国国家半导体公司首席执行官第一次听说摩尔定律是在1975年,那一年EB刚刚创刊,当时他还是英特尔公司的一名年轻工程师;Aart De Geus,Synopsys公司首席执行官于1979年的一次技术研讨会上首次听说摩尔定律,当时他还在读研究生;T．J．Rodgers,赛普拉斯半导体公司首席执行官也是1979年才首次从戈登·摩尔那里听说摩尔定律。

Fine-Grain Sleep Transistor Insertion for Leakage Reduction

A fine-grain sleep transistor insertion technique based on our simplified leakage current and delay models is proposed to reduce leakage current. The key idea is to model the leakage current reduction problem as a mixed-integer linear programming （MLP） problem in order to simultaneously place and size the sleep transistors optimally. Because of better circuit slack utilization, our experimental results show that the MLP model can save leakage by 79.75%, 93.56%, and 94.99% when the circuit slowdown is 0%, 3%, and 5%, respectively. The MLP model also achieves on average 74.79% less area penalty compared to the conventional fixed slowdown method when the circuit slowdown is 7%.

Modeling and Simulation of Photoelectronic Lambda Bipolar Transistor

Based on the region model of lambda bipolar transistor ( LBT), a dividing region theory model of PLBT is set up,simulated and verified. Firstly, the principal operations of different kinds of photoelectronic lambda bipolar transistor ( PLBT) are characterized by a simple circuit model. Through mathematical analysis of the equivalent circuit, the typical characteristics curve is divided into positive resistance, peak, negative resistance and cutoff regions. Secondly, by analyzing and simulating this model, the ratio of MOSFET width to channel length, threshold voltage and common emitter gain are discovered as the main structure parameters that determine the characteristic curves of PLBT. And peak region width, peak current value, negative resistance value and valley voltage value of PLBT can be changed conveniently according to the actual demands by modifying these parameters. Finally comparisons of the characteristics of the fabricated devices and the simu- lation results are made, which show that the analytical results are in agreement with the observed devices characteristics.

STUDY ON THE RELATION BETWEEN STRUCTURE AND HOT CARRIER EFFECT IMMUNITY FOR DEEP SUB-MICRON GROOVED GATE NMOSFET's

Grooved gate structure Metal-Oxide-Semiconductor (MOS) device is consideredas the most promising candidate used in deep and super-deep sub-micron region, for it cansuppress hot carrier effect and short channel effect deeply. Based on the hydrodynamic energytransport model, using two-dimensional device simulator Medici, the relation between structureparameters and hot carrier effect immunity for deep-sub-micron N-channel MOSFET's is studiedand compared with that of counterpart conventional planar device in this paper. The examinedstructure parameters include negative junction depth, concave corner and effective channel length.Simulation results show that grooved gate device can suppress hot carrier effect deeply even indeep sub-micron region. The studies also indicate that hot carrier effect is strongly influencedby the concave corner and channel length for grooved gate device. With the increase of concavecorner, the hot carrier effect in grooved gate MOSFET decreases sharply, and with the reducingof effective channel length, the hot carrier effect becomes large.

Study on Heat Dissipater for High-Power Thyristors in Explosion-Proof Shell

A new type water-cooled heat dissipater for multiple high-power thyristors in explosion-proof shell used in coal mine was designed, and then, the numerical computation of the three-dimensional steady-state temperature distributions under different working conditions for cooling core was conducted in order to understand in detail the heat transfer performance. Based on the computation results, the temperature differences and the maximum heat transfer rates were given. These results of the study on the heat dissipater lay a basis for optimising its structure design and guiding its operation.

A Magnetron Power Supply with Transition-Mode Zero-Voltage-Switching Inverter

This paper presents a transition-mode zero-voltage-switching inverter for the cooker magnetron of household microwave ovens. The inverter drives a leakage transformer to generate the required high voltage and stabilized current. For achieving zero-voltage switching, a transition-mode driver L6561 is utilized to detect the ending of transformer resonance and drive an insulated-gate-bipolar-transistor. As transistor is conducted, rectified direct-current voltage drives the transformer. While transistor is cut off, transformer resonates with a parallel capacitor. Transistor conduction time and magnetron power are controlled with a 16-bit digital signal controller dsPIC30F4011. For widening the working range, transistor conduction time is set to be inversely changed with line-frequency input voltage. To demonstrate the analysis and design of this paper, a 1 kW inverter circuit is built. Experimental results show the feasibility and usefulness of the designed magnetron power supply.

High χ polystyrene-b-polycarbonate for next generation lithography

Over the past half century,the semiconductor chips have deeply influenced our everyday life through increasingly sophisticated electronic products.The central driving force underlying the remarkable evolution in semiconductor industry is Moore’s Law,nowadays referring to a doubling of transistor counts per chip every 18 months.Sustaining Moore’s Law is economically beneficial;while the manufacturing cost per chip has been held constant,

Two-step gate-recess process combining selective wet-etching and digital wet-etching for InAIAs/InGaAs InP-based HEMTs

A two-step gate-recess process combining high selective wet-etching and non-selective digital wet-etching techniques has been proposed for InAlAs/InGaAs InP-based high electron mobility transistors （HEMTs）. High etching-selectivity ratio of InGaAs to InA1As material larger than 100 is achieved by using mixture solution of succinic acid and hydrogen peroxide （H202）. Selective wet-etching is validated in the gate-recess process of InA1As/InGaAs InP-based HEMTs, which proceeds and auto- matically stops at the InA1As barrier layer. The non-selective digital wet-etching process is developed using a separately controlled oxidation/de-oxidation technique, and during each digital etching cycle 1.2 nm InAIAs material is removed. The two-step gate-recess etching technique has been successfully incorporated into device fabrication. Digital wet-etching is repeated for two cycles with about 3 nm InAIAs barrier layer being etched off. InP-based HEMTs have demonstrated superior extrinsic trans- conductance and RF characteristics to devices fabricated during only the selective gate-recess etching process because of the smaller gate to channel distance.

Lattice constant effects of photonic crystals on the extraction of guided mode of GaN based light emitting diodes

We have fabricated a series of square-lattice hole photonic crystal (2PhC) arrays simultaneously at the un-current injection region on a special sample of GaN based light emitting diode (LED) by using focus ion beam milling (FIBM). The lattice constants of the 2PhC arrays vary from 230 to 1500 nm,while the 2PhC arrays have a constant area of about 9 μm×18 μm and a fixed depth of 150±10 nm which approaches but does not penetrate the active layer. Microscopic electroluminescence images and spectral measurements consistently confirm that the top emitting intensities from different 2PhCs are all enhanced compared with the unpatterned region. It is demonstrated that the output coupling of propagating guided modes is realized by the diffracted transmission of the 2PhCs. The enhancement factors of the guided modes compared with the unpatterned region are plotted as function of the lattice constant. It is found that the highest enhancements for the extraction of guided modes were obtained for the lattice constant of 230 and 460 nm of 2PhCs. The results are discussed by the two-dimensional rigorous coupled wave analysis (RCWA).

Is quantum capacitance in graphene a potential hurdle for device scaling？

Transistor size is constantly being reduced to improve performance as well as power consumption. For the channel length to be reduced, the corresponding gate dielectric thickness should also be reduced. Unfortunately, graphene devices are more complicated due to an extra capacitance called quantum capacitance （CQ） which limits the effective gate dielectric reduction. In this work, we analyzed the effect of CQ on device-scaling issues by extracting it from scaling of the channel length of devices. In contrast to previous reports for metal-insulator- metal structures, a practical device structure was used in conjunction with direct radio-frequency field-effect transistor measurements to describe the graphene channels. In order to precisely extract device parameters, we reassessed the equivalent circuit, and concluded that the on-state model should in fact be used. By careful consideration of the underlap region, our device modeling was shown to be in good agreement with the experimental data. CQ contributions to equivalent oxide thickness were analyzed in detail for varying impurity concentrations in graphene. Finally, we were able to demonstrate that despite contributions from CQ, graphene＇s high mobility and low-voltage operation allows for ~raphene channels suitable for next generation transistors.

Effects of Unintended Dopants on I-V Characteristics of the Double-Gate MOSFETs,a Simulation Study

In this paper, we study the effects of an unintended dopant in the channel on the current-voltage char-acteristics of a Double-Gate (DG) Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). Non-Equilibrium Green's Function (NEGF) approach is used. A quantum transport model to calculate the drain current is presented and subthreshold swing and drain induced barrier lowering (DIBL) effect are studied.