传统企业级固态硬盘存储芯片采用外接DRAM(Dynamic Random Access Memory)颗粒的方式来存储闪存地址转换映射表,不仅成本高,占用面积大,还需要设计复杂的掉电保护流程和额外的备电保持电容。利用新型磁旋存储芯片的掉电非易失特性,以及...传统企业级固态硬盘存储芯片采用外接DRAM(Dynamic Random Access Memory)颗粒的方式来存储闪存地址转换映射表,不仅成本高,占用面积大,还需要设计复杂的掉电保护流程和额外的备电保持电容。利用新型磁旋存储芯片的掉电非易失特性,以及密度高、速度快、功耗低、数据保持时间长、可擦写次数无限等特点,提出了一种基于嵌入式磁旋存储芯片的固态硬盘控制器架构方案,能够大大简化控制器芯片的掉电异常流程和备电设计,节省固态硬盘内部的备电电容成本,有效支撑固态硬盘的容量提升。展开更多
In the complex multicore chip system,network on-chip(NoC)is viewed as a kind of system interconnection that can substitute the traditional interconnect networks,which will improve the system performance and communicat...In the complex multicore chip system,network on-chip(NoC)is viewed as a kind of system interconnection that can substitute the traditional interconnect networks,which will improve the system performance and communication efficiency.With regard to the complex and large scale NoC,simple and efficient routing nodes are the critical factors to achieve low-cost and low-congestion communication performance.This paper proposes an unbuffered switch architecture and makes detailed analysis of the mechanism of buffer in the switch architecture.According to the simulation results,the S-mesh using the unbuffered switch architecture is better in terms of the optimal performance in message latency than some typical NoC architectures,such as 2D-mesh,Fat-tree,Butterfly,Octagon and so on.The synthesis results of design compiler indicate that the unbuffered switch has obvious advantages of achieving cost and operating speed for the chips.展开更多
文摘传统企业级固态硬盘存储芯片采用外接DRAM(Dynamic Random Access Memory)颗粒的方式来存储闪存地址转换映射表,不仅成本高,占用面积大,还需要设计复杂的掉电保护流程和额外的备电保持电容。利用新型磁旋存储芯片的掉电非易失特性,以及密度高、速度快、功耗低、数据保持时间长、可擦写次数无限等特点,提出了一种基于嵌入式磁旋存储芯片的固态硬盘控制器架构方案,能够大大简化控制器芯片的掉电异常流程和备电设计,节省固态硬盘内部的备电电容成本,有效支撑固态硬盘的容量提升。
基金Supported by the National High Technology Research and Development Program of China(No.2009AA01Z105)the Ministry of EducationIntel Special Foundation for Information Technology(No.MOE-INTEL-08-05)the Postdoctoral Science Foundation of China(No.20080440942,200902432)
文摘In the complex multicore chip system,network on-chip(NoC)is viewed as a kind of system interconnection that can substitute the traditional interconnect networks,which will improve the system performance and communication efficiency.With regard to the complex and large scale NoC,simple and efficient routing nodes are the critical factors to achieve low-cost and low-congestion communication performance.This paper proposes an unbuffered switch architecture and makes detailed analysis of the mechanism of buffer in the switch architecture.According to the simulation results,the S-mesh using the unbuffered switch architecture is better in terms of the optimal performance in message latency than some typical NoC architectures,such as 2D-mesh,Fat-tree,Butterfly,Octagon and so on.The synthesis results of design compiler indicate that the unbuffered switch has obvious advantages of achieving cost and operating speed for the chips.
