This article introduces a method of achieving high polarization extinction ratio using a subwavelength grating structure on a lithium niobate thin film platform,and the chip is formed on the surface of the lithium nio...This article introduces a method of achieving high polarization extinction ratio using a subwavelength grating structure on a lithium niobate thin film platform,and the chip is formed on the surface of the lithium nio⁃bate thin film.The chip,with a length of just 20μm,achieved a measured polarization extinction ratio of 29 dB at 1550 nm wavelength.This progress not only proves the possibility of achieving a high extinction ratio on a lith⁃ium niobate thin film platform,but also offers important technical references for future work on polarization beam splitters,integrated fiber optic gyroscopes,and so on.展开更多
The reverse generation current under high-gate-voltage stress condition in LDD nMOSFET＇s is studied. We find that the generation current peak decreases as the stress time increases. We ascribe this finding to the dom...The reverse generation current under high-gate-voltage stress condition in LDD nMOSFET＇s is studied. We find that the generation current peak decreases as the stress time increases. We ascribe this finding to the dominating oxide trapped electrons that reduce the effective drain bias, lowering the maximal generation rate. The density of the effective trapped electrons affecting the effective drain bias is calculated with our model.展开更多
A quantum model based on solutions to the Schrodinger-Poisson equations is developed to investigate the device behavior related togate tunneling current for nanoscale MOSFETs with high-k gate stacks. This model can mo...A quantum model based on solutions to the Schrodinger-Poisson equations is developed to investigate the device behavior related togate tunneling current for nanoscale MOSFETs with high-k gate stacks. This model can model various MOS device structures with combinations of high-k dielectric materials and multilayer gate stacks,revealing quantum effects on the device performance. Comparisons are made for gate current behavior between nMOSFET and pMOSFET high- k gate stack structures. The results presented are consistent with experimental data, whereas a new finding for an optimum nitrogen content in HfSiON gate dielectric requires further experimental verifications.展开更多
A direct tunneling model through gate dielectric s in CMOS devices in the frame of WKB approximation is reported.In the model,an im proved one-band effective mass approximation is used for the hole quantization, wher...A direct tunneling model through gate dielectric s in CMOS devices in the frame of WKB approximation is reported.In the model,an im proved one-band effective mass approximation is used for the hole quantization, where valence band mixing is taken into account.By comparing to the experiments, the model is demonstrated to be applicable to both electron and hole tunneling c urrents in CMOS devices.The effect of the dispersion in oxide energy gap on the tunneling current is also studied.This model can be further extended to study th e direct tunneling current in future high-k materials.展开更多
200nm gate-length GaAs-based InAlAs/InGaAs MHEMTs are fabricated by MBE epitaxial material and EBL （electron beam lithography） technology. Ti/Pt/Au is evaporated to form gate metals. A T-shaped gate is produced usin...200nm gate-length GaAs-based InAlAs/InGaAs MHEMTs are fabricated by MBE epitaxial material and EBL （electron beam lithography） technology. Ti/Pt/Au is evaporated to form gate metals. A T-shaped gate is produced using a novel PMMA/PMGI/PMMA trilayer resist structure to decrease parasitic capacitance and parasitic resistance of the gate. Excellent DC and RF performances are obtained and the transconductance （gm） ,maximum saturation drain current density （Joss）, threshold voltage （ VT）, current cut-off frequency （fT） , and maximum oscillation frequency （fmax） of InAlAs/ InGaAs MHEMTs are 510mS/mm,605mA/mm, -1.8V, 110GHz, and 72GHz, respectively.展开更多
A novel low-cost sub-50nm poly-Si gate patterning technology is proposed and experimentally demonstrated.The technology is resolution-independent,ie.,it does not contain any critical photolithographic steps.The nano-s...A novel low-cost sub-50nm poly-Si gate patterning technology is proposed and experimentally demonstrated.The technology is resolution-independent,ie.,it does not contain any critical photolithographic steps.The nano-scale masking pattern for gate formation is formed according to the image transfer of an edge-defined spacer.Experimental results reveal that the resultant gate length,about 75 to 85 percent of the thickness,is determined by the thickness of the film to form the spacer.From SEM photograph,the cross-section of the poly-Si gate is seen to be an inverted-trapezoid,which is useful to reduce the gate resistance.展开更多
The front gate interface and oxide traps induced by hot carrier stress in SOI NMOSFETs are studied.Based on a new forward gated diode technique,the R G current originating from the front interface traps is me...The front gate interface and oxide traps induced by hot carrier stress in SOI NMOSFETs are studied.Based on a new forward gated diode technique,the R G current originating from the front interface traps is measured,and then the densities of the interface and oxide traps are separated independently.The experimental results show that the hot carrier stress of front channel not only results in the strong generation of the front interface traps,but also in the significant oxide traps.These two kinds of traps have similar characteristic in increasing with the hot carrier stress time.This analysis allows one to obtain a clear physical picture of the effects of the hot carrier stress on the generating of interface and oxide traps,which help to understand the degradation and reliability of the SOI MOSFETs.展开更多
In order to minimize the hot-carrier effect（HCE）and maintain on-state performance in the high voltage N-type lateral double diffused MOS（N-LDMOS）, an optimized device structure with step gate oxide is proposed. Co...In order to minimize the hot-carrier effect（HCE）and maintain on-state performance in the high voltage N-type lateral double diffused MOS（N-LDMOS）, an optimized device structure with step gate oxide is proposed. Compared with the conventional configuration, the electric field under the gate along the Si-SiO2 interface in the presented N-LDMOS can be greatly reduced, which favors reducing the hot-carrier degradation. The step gate oxide can be achieved by double gate oxide growth, which is commonly used in some smart power ICs. The differences in hot-carrier degradations between the novel structure and the conventional structure are investigated and analyzed by 2D technology computer-aided design（TCAD）numerical simulations, and the optimal length of the thick gate oxide part in the novel N-LDMOS device can also be acquired on the basis of maintaining the characteristic parameters of the conventional device. Finally, the practical degradation measurements of some characteristic parameters can also be carried out. It is found that the hot-carrier degradation of the novel N-LDMOS device can be improved greatly.展开更多
Hot carrier effects of p MOSFETs with different oxide thicknesses are studied in low gate voltage range.All electrical parameters follow a power law relationship with stress time,but degradation slope is dependent ...Hot carrier effects of p MOSFETs with different oxide thicknesses are studied in low gate voltage range.All electrical parameters follow a power law relationship with stress time,but degradation slope is dependent on gate voltage.For the devices with thicker oxides,saturated drain current degradation has a close relationship with the product of gate current and electron fluence.For small dimensional devices,saturated drain current degradation has a close relationship with the electron fluence.This degradation model is valid for p MOSFETs with 0 25μm channel length and different gate oxide thicknesses.展开更多
The on-resistance degradations of the p-type lateral extended drain MOS transistor （pLEDMOS） with thick gate oxide under different hot carrier stress conditions are different, which has been experimentally investiga...The on-resistance degradations of the p-type lateral extended drain MOS transistor （pLEDMOS） with thick gate oxide under different hot carrier stress conditions are different, which has been experimentally investigated. This difference results from the interface trap generation and the hot electron injection, and trapping into the thick gate oxide and field oxide of the pLEDMOS transistor. An improved method to reduce the on-resistance degradations is also presented, which uses the field oxide as the gate oxide instead of the thick gate oxide. The effects are analyzed with a MEDICI simulator.展开更多
A dual-wavelength erbium doped fiber laser with a tilted fiber Bragg grating and photonic crystal fiber is proposed and demonstrated. In the laser, a 2W EDFA provides gain for all the laser lines; the highly nonlinear...A dual-wavelength erbium doped fiber laser with a tilted fiber Bragg grating and photonic crystal fiber is proposed and demonstrated. In the laser, a 2W EDFA provides gain for all the laser lines; the highly nonlinear photonic crystal fiber introduces dynamic energy transfer between the two wavelengths caused by four wave mixing effect, so that a stable dual- wavelength oscillation at room temperature is implemented. Different switching modes can be achieved by adjusting the lateral offset between the fiber grating and the guiding single mode fiber or by varying the state of polarization in the laser cavity. The maximum of output power of the laser has reached 314mW.展开更多
A Smith-Purcell （SP） free electron laser （FEL） ,composed of a metallic diffraction flat grating,an open cylindrical mirror cavity and a relativistic sheet electron beam with moderate energy, is presented. The char...A Smith-Purcell （SP） free electron laser （FEL） ,composed of a metallic diffraction flat grating,an open cylindrical mirror cavity and a relativistic sheet electron beam with moderate energy, is presented. The characteristics of this device are studied by theoretical analysis,experimental measurements and particle-in-cell （PIO） simulation method. Results indicate that the coherent radiation with an output peak power up to 50 MW at millimeter wavelengths can be generated by using relativistic electron beam of moderate energy.展开更多
Nitrogen implantation in silicon substrate at fixed energy of 35keV and split dose of 10 14～5×10 14cm -2 is performed before gate oxidation.The experiment results indicate that with the increasing of implanta...Nitrogen implantation in silicon substrate at fixed energy of 35keV and split dose of 10 14～5×10 14cm -2 is performed before gate oxidation.The experiment results indicate that with the increasing of implantation dose of nitrogen,oxidation rate of gate decreases.The retardation in oxide growth is weakened due to thermal annealing after nitrogen implantation.After nitrogen is implanted at the dose of 2×10 14cm -2,initial O 2 injection method which is composed of an O 2 injection/N 2 annealing/main oxidation,is applied for preparation of 3 4nm gate oxide.Compared with the control process,which is composed of N 2 annealing/main oxidation,initial O 2 injection process suppresses leakage current of the gate oxide.But Q bd and HF C-V characteristics are almost identical for the samples fabricated by two different oxidation processes.展开更多
基金Supported by Beijing Natural Science Foundation(4242062)and the Youth Innovation Promotion Association,CAS(2021108)。
文摘This article introduces a method of achieving high polarization extinction ratio using a subwavelength grating structure on a lithium niobate thin film platform,and the chip is formed on the surface of the lithium nio⁃bate thin film.The chip,with a length of just 20μm,achieved a measured polarization extinction ratio of 29 dB at 1550 nm wavelength.This progress not only proves the possibility of achieving a high extinction ratio on a lith⁃ium niobate thin film platform,but also offers important technical references for future work on polarization beam splitters,integrated fiber optic gyroscopes,and so on.
文摘The reverse generation current under high-gate-voltage stress condition in LDD nMOSFET＇s is studied. We find that the generation current peak decreases as the stress time increases. We ascribe this finding to the dominating oxide trapped electrons that reduce the effective drain bias, lowering the maximal generation rate. The density of the effective trapped electrons affecting the effective drain bias is calculated with our model.
文摘A quantum model based on solutions to the Schrodinger-Poisson equations is developed to investigate the device behavior related togate tunneling current for nanoscale MOSFETs with high-k gate stacks. This model can model various MOS device structures with combinations of high-k dielectric materials and multilayer gate stacks,revealing quantum effects on the device performance. Comparisons are made for gate current behavior between nMOSFET and pMOSFET high- k gate stack structures. The results presented are consistent with experimental data, whereas a new finding for an optimum nitrogen content in HfSiON gate dielectric requires further experimental verifications.
文摘A direct tunneling model through gate dielectric s in CMOS devices in the frame of WKB approximation is reported.In the model,an im proved one-band effective mass approximation is used for the hole quantization, where valence band mixing is taken into account.By comparing to the experiments, the model is demonstrated to be applicable to both electron and hole tunneling c urrents in CMOS devices.The effect of the dispersion in oxide energy gap on the tunneling current is also studied.This model can be further extended to study th e direct tunneling current in future high-k materials.
基金the State Key Development Program for Basic Research of China(No.G2002CB311901)the Equipment Investigation Program in Advance(No.61501050401C)the Dean Fund of the Institute of Microelectronics,Chinese Academy of Sciences(No.O6SB124004)~~
文摘200nm gate-length GaAs-based InAlAs/InGaAs MHEMTs are fabricated by MBE epitaxial material and EBL （electron beam lithography） technology. Ti/Pt/Au is evaporated to form gate metals. A T-shaped gate is produced using a novel PMMA/PMGI/PMMA trilayer resist structure to decrease parasitic capacitance and parasitic resistance of the gate. Excellent DC and RF performances are obtained and the transconductance （gm） ,maximum saturation drain current density （Joss）, threshold voltage （ VT）, current cut-off frequency （fT） , and maximum oscillation frequency （fmax） of InAlAs/ InGaAs MHEMTs are 510mS/mm,605mA/mm, -1.8V, 110GHz, and 72GHz, respectively.
文摘A novel low-cost sub-50nm poly-Si gate patterning technology is proposed and experimentally demonstrated.The technology is resolution-independent,ie.,it does not contain any critical photolithographic steps.The nano-scale masking pattern for gate formation is formed according to the image transfer of an edge-defined spacer.Experimental results reveal that the resultant gate length,about 75 to 85 percent of the thickness,is determined by the thickness of the film to form the spacer.From SEM photograph,the cross-section of the poly-Si gate is seen to be an inverted-trapezoid,which is useful to reduce the gate resistance.
文摘The front gate interface and oxide traps induced by hot carrier stress in SOI NMOSFETs are studied.Based on a new forward gated diode technique,the R G current originating from the front interface traps is measured,and then the densities of the interface and oxide traps are separated independently.The experimental results show that the hot carrier stress of front channel not only results in the strong generation of the front interface traps,but also in the significant oxide traps.These two kinds of traps have similar characteristic in increasing with the hot carrier stress time.This analysis allows one to obtain a clear physical picture of the effects of the hot carrier stress on the generating of interface and oxide traps,which help to understand the degradation and reliability of the SOI MOSFETs.
基金The Natural Science Foundation of Jiangsu Province(No.BK2008287)the Preresearch Project of the National Natural Science Foundation of Southeast University(No.XJ2008312)
文摘In order to minimize the hot-carrier effect（HCE）and maintain on-state performance in the high voltage N-type lateral double diffused MOS（N-LDMOS）, an optimized device structure with step gate oxide is proposed. Compared with the conventional configuration, the electric field under the gate along the Si-SiO2 interface in the presented N-LDMOS can be greatly reduced, which favors reducing the hot-carrier degradation. The step gate oxide can be achieved by double gate oxide growth, which is commonly used in some smart power ICs. The differences in hot-carrier degradations between the novel structure and the conventional structure are investigated and analyzed by 2D technology computer-aided design（TCAD）numerical simulations, and the optimal length of the thick gate oxide part in the novel N-LDMOS device can also be acquired on the basis of maintaining the characteristic parameters of the conventional device. Finally, the practical degradation measurements of some characteristic parameters can also be carried out. It is found that the hot-carrier degradation of the novel N-LDMOS device can be improved greatly.
文摘Hot carrier effects of p MOSFETs with different oxide thicknesses are studied in low gate voltage range.All electrical parameters follow a power law relationship with stress time,but degradation slope is dependent on gate voltage.For the devices with thicker oxides,saturated drain current degradation has a close relationship with the product of gate current and electron fluence.For small dimensional devices,saturated drain current degradation has a close relationship with the electron fluence.This degradation model is valid for p MOSFETs with 0 25μm channel length and different gate oxide thicknesses.
文摘The on-resistance degradations of the p-type lateral extended drain MOS transistor （pLEDMOS） with thick gate oxide under different hot carrier stress conditions are different, which has been experimentally investigated. This difference results from the interface trap generation and the hot electron injection, and trapping into the thick gate oxide and field oxide of the pLEDMOS transistor. An improved method to reduce the on-resistance degradations is also presented, which uses the field oxide as the gate oxide instead of the thick gate oxide. The effects are analyzed with a MEDICI simulator.
文摘A dual-wavelength erbium doped fiber laser with a tilted fiber Bragg grating and photonic crystal fiber is proposed and demonstrated. In the laser, a 2W EDFA provides gain for all the laser lines; the highly nonlinear photonic crystal fiber introduces dynamic energy transfer between the two wavelengths caused by four wave mixing effect, so that a stable dual- wavelength oscillation at room temperature is implemented. Different switching modes can be achieved by adjusting the lateral offset between the fiber grating and the guiding single mode fiber or by varying the state of polarization in the laser cavity. The maximum of output power of the laser has reached 314mW.
文摘A Smith-Purcell （SP） free electron laser （FEL） ,composed of a metallic diffraction flat grating,an open cylindrical mirror cavity and a relativistic sheet electron beam with moderate energy, is presented. The characteristics of this device are studied by theoretical analysis,experimental measurements and particle-in-cell （PIO） simulation method. Results indicate that the coherent radiation with an output peak power up to 50 MW at millimeter wavelengths can be generated by using relativistic electron beam of moderate energy.
文摘Nitrogen implantation in silicon substrate at fixed energy of 35keV and split dose of 10 14～5×10 14cm -2 is performed before gate oxidation.The experiment results indicate that with the increasing of implantation dose of nitrogen,oxidation rate of gate decreases.The retardation in oxide growth is weakened due to thermal annealing after nitrogen implantation.After nitrogen is implanted at the dose of 2×10 14cm -2,initial O 2 injection method which is composed of an O 2 injection/N 2 annealing/main oxidation,is applied for preparation of 3 4nm gate oxide.Compared with the control process,which is composed of N 2 annealing/main oxidation,initial O 2 injection process suppresses leakage current of the gate oxide.But Q bd and HF C-V characteristics are almost identical for the samples fabricated by two different oxidation processes.
