Fabrication of enhancement-mode high electron mobility transistors on AlGaN/GaN heterostructures grown on sapphire substrates is reported. These devices with 1.2μm gate-length,4mm space between source and drain,and 1...Fabrication of enhancement-mode high electron mobility transistors on AlGaN/GaN heterostructures grown on sapphire substrates is reported. These devices with 1.2μm gate-length,4mm space between source and drain,and 15nm recessed-gate depth exhibit a maximum drain current of 332mA/mm at 3V, a maximum transconductance of 221mS/mm, a threshold voltage of 0.57V, ft of 5.2GHz, and fmax of 9.3GHz. A dielectric layer formed unintentionally during recessedgate etching is confirmed by contrasting the Schottky I-V characteristics of pre-etching and post-etching. The frequency characteristics and subthreshold characteristics of the devices are studied in detail.展开更多
In order to suppress drain-induced barrier lowering in dual material gate SOI MOSFETs,halo doping is used in the channel near the source. Two-dimensional analytical models of surface potential and threshold voltage fo...In order to suppress drain-induced barrier lowering in dual material gate SOI MOSFETs,halo doping is used in the channel near the source. Two-dimensional analytical models of surface potential and threshold voltage for the novel SOI MOSFET are developed based on the explicit solution of the two-dimensional Poisson＇s equation. Its characteristic improvement is investigated. It is concluded that the novel structure exhibits better suppression of drain-induced barrier lowering and higher carrier transport efficiency than conventional dual material gate SOI MOSFETs. Its drain-induced barrier lowering decreases with increasing halo doping concentration but does not change monotonically with halo length. The analytical models agree well with the two-dimensional device simulator MEDICI.展开更多
A quasi two-dimensional （2D） analytical model of a double-gate （DG） MOSFET with Schottky source/drain is developed based on the Poisson equation.The 2D potential distribution in the channel is calculated.An expres...A quasi two-dimensional （2D） analytical model of a double-gate （DG） MOSFET with Schottky source/drain is developed based on the Poisson equation.The 2D potential distribution in the channel is calculated.An expression for threshold voltage for a short-channel DG MOSFET with Schottky S/D is also presented by defining the turn-on condition.The results of the model are verified by the numerical simulator DESSIS-ISE.展开更多
The tunnel field-effect transistor(TFET) is a potential candidate for the post-CMOS era.As one of the most important electrical parameters of a device,double gate TFET(DG-TFET) gate threshold voltage was studied.First...The tunnel field-effect transistor(TFET) is a potential candidate for the post-CMOS era.As one of the most important electrical parameters of a device,double gate TFET(DG-TFET) gate threshold voltage was studied.First,a numerical simulation study of transfer characteristic and gate threshold voltage in DG-TFET was reported.Then,a simple analytical model for DG-TFET gate threshold voltage VTG was built by solving quasi-two-dimensional Poisson equation in Si film.The model as a function of the drain voltage,the Si layer thickness,the gate length and the gate dielectric was discussed.It is shown that the proposed model is consistent with the simulation results.This model should be useful for further investigation of performance of circuits containing TFETs.展开更多
基金the Key Programof the National Natural Science Foundation of China(No.60736033)~~
文摘Fabrication of enhancement-mode high electron mobility transistors on AlGaN/GaN heterostructures grown on sapphire substrates is reported. These devices with 1.2μm gate-length,4mm space between source and drain,and 15nm recessed-gate depth exhibit a maximum drain current of 332mA/mm at 3V, a maximum transconductance of 221mS/mm, a threshold voltage of 0.57V, ft of 5.2GHz, and fmax of 9.3GHz. A dielectric layer formed unintentionally during recessedgate etching is confirmed by contrasting the Schottky I-V characteristics of pre-etching and post-etching. The frequency characteristics and subthreshold characteristics of the devices are studied in detail.
文摘In order to suppress drain-induced barrier lowering in dual material gate SOI MOSFETs,halo doping is used in the channel near the source. Two-dimensional analytical models of surface potential and threshold voltage for the novel SOI MOSFET are developed based on the explicit solution of the two-dimensional Poisson＇s equation. Its characteristic improvement is investigated. It is concluded that the novel structure exhibits better suppression of drain-induced barrier lowering and higher carrier transport efficiency than conventional dual material gate SOI MOSFETs. Its drain-induced barrier lowering decreases with increasing halo doping concentration but does not change monotonically with halo length. The analytical models agree well with the two-dimensional device simulator MEDICI.
文摘A quasi two-dimensional （2D） analytical model of a double-gate （DG） MOSFET with Schottky source/drain is developed based on the Poisson equation.The 2D potential distribution in the channel is calculated.An expression for threshold voltage for a short-channel DG MOSFET with Schottky S/D is also presented by defining the turn-on condition.The results of the model are verified by the numerical simulator DESSIS-ISE.
基金Project(P140c090303110c0904)supported by NLAIC Research Fund,ChinaProject(JY0300122503)supported by the Research Fund for the Doctoral Program of Higher Education of China+1 种基金Projects(K5051225014,K5051225004)supported by the Fundamental Research Funds for the Central Universities,ChinaProject(2010JQ8008)supported by the Natural Science Basic Research Plan in Shaanxi Province of China
文摘The tunnel field-effect transistor(TFET) is a potential candidate for the post-CMOS era.As one of the most important electrical parameters of a device,double gate TFET(DG-TFET) gate threshold voltage was studied.First,a numerical simulation study of transfer characteristic and gate threshold voltage in DG-TFET was reported.Then,a simple analytical model for DG-TFET gate threshold voltage VTG was built by solving quasi-two-dimensional Poisson equation in Si film.The model as a function of the drain voltage,the Si layer thickness,the gate length and the gate dielectric was discussed.It is shown that the proposed model is consistent with the simulation results.This model should be useful for further investigation of performance of circuits containing TFETs.
