A new method of constructing regular low-density parity-check (LDPC) codes was proposed. And the novel class of LDPC codes was applied in a coded orthogonal frequency division multiplexing (OFDM) system. This method e...A new method of constructing regular low-density parity-check (LDPC) codes was proposed. And the novel class of LDPC codes was applied in a coded orthogonal frequency division multiplexing (OFDM) system. This method extended the class of LDPC codes which could be constructed from shifted identity matrices. The method could avoid short cycles in Tanner graphs with simple inequation in the construction of shifting identity matrices, which made the girth of Tanner graphs 8. Because of the quasicyclic structure and the inherent block configuration of parity-check matrices, the encoders and the decoders were practically feasible. They were linear-time encodable and decodable. The LDPC codes proposed had various code rates, ranging from low to high. They performed excellently with iterative decoding and demonstrate better performance than other regular LDPC codes in OFDM systems.展开更多
A modified Benes network is proposed to be used as an optimal shuffle network in worldwide interoperability for microwave access (WiMAX) low density parity check (LDPC) decoders, When the size of the input is not ...A modified Benes network is proposed to be used as an optimal shuffle network in worldwide interoperability for microwave access (WiMAX) low density parity check (LDPC) decoders, When the size of the input is not a power of two, the modified Benes network can achieve the most optimal performance. This modified Benes network is non-blocking and can perform any sorts of permutations, so it can support 19 modes specified in the WiMAX system. Furthermore, an efficient algorithm to generate the control signals for all the 2 × 2 switches in this network is derived, which can reduce the hardware complexity and overall latency of the modified Benes network. Synthesis results show that the proposed control signal generator can save 25.4% chip area and the overall network latency can be reduced by 36. 2%.展开更多
Quasi-cyclic low-density parity-check (QC-LDPC) codes can be constructed conveniently by cyclic lifting of protographs. For the purpose of eliminating short cycles in the Tanner graph to guarantee performance, first...Quasi-cyclic low-density parity-check (QC-LDPC) codes can be constructed conveniently by cyclic lifting of protographs. For the purpose of eliminating short cycles in the Tanner graph to guarantee performance, first an algorithm to enumerate the harmful short cycles in the protograph is designed, and then a greedy algorithm is proposed to assign proper permutation shifts to the circulant permutation submatrices in the parity check matrix after lifting. Compared with the existing deterministic edge swapping (DES) algorithms, the proposed greedy algorithm adds more constraints in the assignment of permutation shifts to improve performance. Simulation results verify that it outperforms DES in reducing short cycles. In addition, it is proved that the parity check matrices of the cyclic lifted QC-LDPC codes can be transformed into block lower triangular ones when the lifting factor is a power of 2. Utilizing this property, the QC- LDPC codes can be encoded by preprocessing the base matrices, which reduces the encoding complexity to a large extent.展开更多
Due to the ubiquitous open air links and complex electromagnetic environment in the satellite communications,how to ensure the security and reliability of the information through the satellite communications is an urg...Due to the ubiquitous open air links and complex electromagnetic environment in the satellite communications,how to ensure the security and reliability of the information through the satellite communications is an urgent problem.This paper combines the AES(Advanced Encryption Standard) with LDPC(Low Density Parity Check Code) to design a secure and reliable error correction method — SEEC(Satellite Encryption and Error Correction).This method selects the LDPC codes,which is suitable for satellite communications,and uses the AES round key to control the encoding process,at the same time,proposes a new algorithm of round key generation.Based on a fairly good property in error correction in satellite communications,the method improves the security of the system,achieves a shorter key size,and then makes the key management easier.Eventually,the method shows a great error correction capability and encryption effect by the MATLAB simulation.展开更多
Non-uniform quantization for messages in Low-Density Parity-Check(LDPC)decoding canreduce implementation complexity and mitigate performance loss.But the distribution of messagesvaries in the iterative decoding.This l...Non-uniform quantization for messages in Low-Density Parity-Check(LDPC)decoding canreduce implementation complexity and mitigate performance loss.But the distribution of messagesvaries in the iterative decoding.This letter proposes a variable non-uniform quantized Belief Propaga-tion(BP)algorithm.The BP decoding is analyzed by density evolution with Gaussian approximation.Since the probability density of messages can be well approximated by Gaussian distribution,by theunbiased estimation of variance,the distribution of messages can be tracked during the iteration.Thusthe non-uniform quantization scheme can be optimized to minimize the distortion.Simulation resultsshow that the variable non-uniform quantization scheme can achieve better error rate performance andfaster decoding convergence than the conventional non-uniform quantization and uniform quantizationschemes.展开更多
A novel design and implementation of an attendance checking node for coal mines based on the CAN bus is presented in this paper. Hardware circuits and programming methods for the attendance checking node are discussed...A novel design and implementation of an attendance checking node for coal mines based on the CAN bus is presented in this paper. Hardware circuits and programming methods for the attendance checking node are discussed,including the single-chip computer with CAN controller AT89C51CC03,the CAN bus transceiver TJA1050,the large capacity DataFlash memory,the real-time clock DS1302,the voice chip ISD2560 and the card-reading circuit in Wie-gand format. All the extended hardware satisfies the requirements for intrinsically safe circuits (GB3836.4-2000) and intrinsically safe authentication promoted by the national explosion-proof institute. Further,the software programming methods for the CAN controller (AT89C51CC03) and the implementation of the CAN communications protocol are presented as well.展开更多
Abstract: The layered decoding algorithm has been widely used in the implementation of Low Density Parity Check (LDPC) decoders, due to its high convergence speed. However, the pipeline operation of the layered dec...Abstract: The layered decoding algorithm has been widely used in the implementation of Low Density Parity Check (LDPC) decoders, due to its high convergence speed. However, the pipeline operation of the layered decoder may introduce memory access conflicts, which heavily deteriorates the decoder throughput. To essentially deal with the issue of memory access conflicts,展开更多
This paper is concerned with (3,n) and (4,n) regular quasi-cyclic Low Density Parity Check (LDPC) code constructions from elementary number theory.Given the column weight,we determine the shift values of the circulant...This paper is concerned with (3,n) and (4,n) regular quasi-cyclic Low Density Parity Check (LDPC) code constructions from elementary number theory.Given the column weight,we determine the shift values of the circulant permutation matrices via arithmetic analysis.The proposed constructions of quasi-cyclic LDPC codes achieve the following main advantages simultaneously:1) our methods are constructive in the sense that we avoid any searching process;2) our methods ensure no four or six cycles in the bipartite graphs corresponding to the LDPC codes;3) our methods are direct constructions of quasi-cyclic LDPC codes which do not use any other quasi-cyclic LDPC codes of small length like component codes or any other algorithms/cyclic codes like building block;4)the computations of the parameters involved are based on elementary number theory,thus very simple and fast.Simulation results show that the constructed regular codes of high rates perform almost 1.25 dB above Shannon limit and have no error floor down to the bit-error rate of 10-6.展开更多
In this paper, we present a Joint Source-Channel Decoding algorithm (JSCD) for Low-Density Parity Check (LDPC) codes by modifying the Sum-Product Algorithm (SPA) to account for the source redun-dancy, which results fr...In this paper, we present a Joint Source-Channel Decoding algorithm (JSCD) for Low-Density Parity Check (LDPC) codes by modifying the Sum-Product Algorithm (SPA) to account for the source redun-dancy, which results from the neighbouring Huffman coded bits. Simulations demonstrate that in the presence of source redundancy, the proposed algorithm gives better performance than the Separate Source and Channel Decoding algorithm (SSCD).展开更多
In order to guarantee reliable data transmission, powerful channel coding techniques are usually required in noncoherent ultra-wideband(UWB) communication systems. Accordingly, several forward error correction(FEC) co...In order to guarantee reliable data transmission, powerful channel coding techniques are usually required in noncoherent ultra-wideband(UWB) communication systems. Accordingly, several forward error correction(FEC) codes, such as Reed-Solomon and convolutional codes have been used in noncoherent UWB systems to improve the bit error rate(BER) performance. In this paper, low-density parity-check(LDPC) codes are further studied as more powerful FEC candidates for noncoherent UWB systems. Two LDPC codes and the corresponding decoding procedures are presented for noncoherent UWB systems. Moreover, performance comparison between the LDPC codes and other FEC codes are provided for three major noncoherent UWB communication systems, namely, noncoherent pulse position modulation(NC-PPM), transmitted reference(TR) and transmitted reference pulse cluster(TRPC). Both theoretical analysis and simulation results show that the two investigated LDPC codes outperform other existing FEC codes with limited penalty in terms of complexity and therefore they are promising FEC candidates for noncoherent UWB systems with low-cost and low-power consumption.展开更多
This paper describes an in-house developed language tool called VPerl used in developing a 250 MHz 32-bit high-performance low power embedded CPU core. The authors showed that use of this tool can compress the Verilog...This paper describes an in-house developed language tool called VPerl used in developing a 250 MHz 32-bit high-performance low power embedded CPU core. The authors showed that use of this tool can compress the Verilog code by more than a factor of 5, increase the efficiency of the front-end design, reduce the bug rate significantly. This tool can be used to enhance the reusability of an intellectual property model, and facilitate porting design for different platforms.展开更多
A low density parity check(LDPC)encoder with the codes of(8176,7154)and encoding rate of 7/8 under CCSDS standard for near space communication is designed.Based on LDPC encoding theory,the FPGA-based coding algorithm ...A low density parity check(LDPC)encoder with the codes of(8176,7154)and encoding rate of 7/8 under CCSDS standard for near space communication is designed.Based on LDPC encoding theory,the FPGA-based coding algorithm is designed.Based on the characteristics of LDPC generating matrix,the cyclic shift register is introduced as the core of the encoding circuit,and the shift-register-Adder-Accumulator(SRAA)structure is adopted to realize the fast calculation of matrix multiplication,so as to construct the encoding module with partial parallel encoding circuit as the core.In addition,the serial port input and output module,RAM storage module and control module are also designed,which together constitute the encoder system.The design scheme is implemented by FPGA hardware and verified by simulation and experiment.The results show that the test results of the designed LDPC encoder are consistent with the theoretical results.Therefore,the coding system is practical,and the design method is simple and efficient.展开更多
In this paper, based on the characteristics of polar codes, a new decode-and-forward strategy called generalized partial information relaying protocol is proposed for degraded multiple-relay networks with orthogonal r...In this paper, based on the characteristics of polar codes, a new decode-and-forward strategy called generalized partial information relaying protocol is proposed for degraded multiple-relay networks with orthogonal receiver components(MRNORCs). In such a protocol, with the help of partial information from previous nodes, each relay node tries to recover the received source message and re-encodes part of the decoded message for transmission to satisfy the decoding requirements for the following relay node or the destination node. In order to construct practical polar codes, the nested structures are developed based on this protocol and the information sets corresponding to the partial messages forwarded are also calculated. The proposed scheme is proved to be capable of achieving the theoretical capacity of the degraded MRN-ORCs while still retains the low-complexity feature of polar codes. We perform simulations to testify the practicability of the proposed scheme and compare polar codes by using successive-cancellation list decoder(SCLD) with traditional low-density parity-check(LDPC) codes. The results show that the obtained polar codes provide significant gain.展开更多
文摘A new method of constructing regular low-density parity-check (LDPC) codes was proposed. And the novel class of LDPC codes was applied in a coded orthogonal frequency division multiplexing (OFDM) system. This method extended the class of LDPC codes which could be constructed from shifted identity matrices. The method could avoid short cycles in Tanner graphs with simple inequation in the construction of shifting identity matrices, which made the girth of Tanner graphs 8. Because of the quasicyclic structure and the inherent block configuration of parity-check matrices, the encoders and the decoders were practically feasible. They were linear-time encodable and decodable. The LDPC codes proposed had various code rates, ranging from low to high. They performed excellently with iterative decoding and demonstrate better performance than other regular LDPC codes in OFDM systems.
基金The National Natural Science Foundation of China(No.60871079)
文摘A modified Benes network is proposed to be used as an optimal shuffle network in worldwide interoperability for microwave access (WiMAX) low density parity check (LDPC) decoders, When the size of the input is not a power of two, the modified Benes network can achieve the most optimal performance. This modified Benes network is non-blocking and can perform any sorts of permutations, so it can support 19 modes specified in the WiMAX system. Furthermore, an efficient algorithm to generate the control signals for all the 2 × 2 switches in this network is derived, which can reduce the hardware complexity and overall latency of the modified Benes network. Synthesis results show that the proposed control signal generator can save 25.4% chip area and the overall network latency can be reduced by 36. 2%.
基金The National Key Technology R&D Program of China during the 12th Five-Year Plan Period(No.2012BAH15B00)
文摘Quasi-cyclic low-density parity-check (QC-LDPC) codes can be constructed conveniently by cyclic lifting of protographs. For the purpose of eliminating short cycles in the Tanner graph to guarantee performance, first an algorithm to enumerate the harmful short cycles in the protograph is designed, and then a greedy algorithm is proposed to assign proper permutation shifts to the circulant permutation submatrices in the parity check matrix after lifting. Compared with the existing deterministic edge swapping (DES) algorithms, the proposed greedy algorithm adds more constraints in the assignment of permutation shifts to improve performance. Simulation results verify that it outperforms DES in reducing short cycles. In addition, it is proved that the parity check matrices of the cyclic lifted QC-LDPC codes can be transformed into block lower triangular ones when the lifting factor is a power of 2. Utilizing this property, the QC- LDPC codes can be encoded by preprocessing the base matrices, which reduces the encoding complexity to a large extent.
基金supported by the National 863 Project of China under Grant No.2012AA01A509,No.2012AA120800
文摘Due to the ubiquitous open air links and complex electromagnetic environment in the satellite communications,how to ensure the security and reliability of the information through the satellite communications is an urgent problem.This paper combines the AES(Advanced Encryption Standard) with LDPC(Low Density Parity Check Code) to design a secure and reliable error correction method — SEEC(Satellite Encryption and Error Correction).This method selects the LDPC codes,which is suitable for satellite communications,and uses the AES round key to control the encoding process,at the same time,proposes a new algorithm of round key generation.Based on a fairly good property in error correction in satellite communications,the method improves the security of the system,achieves a shorter key size,and then makes the key management easier.Eventually,the method shows a great error correction capability and encryption effect by the MATLAB simulation.
基金the Aerospace Technology Support Foun-dation of China(No.J04-2005040).
文摘Non-uniform quantization for messages in Low-Density Parity-Check(LDPC)decoding canreduce implementation complexity and mitigate performance loss.But the distribution of messagesvaries in the iterative decoding.This letter proposes a variable non-uniform quantized Belief Propaga-tion(BP)algorithm.The BP decoding is analyzed by density evolution with Gaussian approximation.Since the probability density of messages can be well approximated by Gaussian distribution,by theunbiased estimation of variance,the distribution of messages can be tracked during the iteration.Thusthe non-uniform quantization scheme can be optimized to minimize the distortion.Simulation resultsshow that the variable non-uniform quantization scheme can achieve better error rate performance andfaster decoding convergence than the conventional non-uniform quantization and uniform quantizationschemes.
基金Projects 50674086 supported by the National Natural Science Foundation of ChinaBS2006002 by the Society Development Science and Technology Planof Jiangsu Province20060290508 by the Doctoral Foundation of Ministry of Education of China
文摘A novel design and implementation of an attendance checking node for coal mines based on the CAN bus is presented in this paper. Hardware circuits and programming methods for the attendance checking node are discussed,including the single-chip computer with CAN controller AT89C51CC03,the CAN bus transceiver TJA1050,the large capacity DataFlash memory,the real-time clock DS1302,the voice chip ISD2560 and the card-reading circuit in Wie-gand format. All the extended hardware satisfies the requirements for intrinsically safe circuits (GB3836.4-2000) and intrinsically safe authentication promoted by the national explosion-proof institute. Further,the software programming methods for the CAN controller (AT89C51CC03) and the implementation of the CAN communications protocol are presented as well.
基金the National Natural Science Foundation of China,the National Key Basic Research Program of China,The authors would like to thank all project partners for their valuable contributions and feedbacks
文摘Abstract: The layered decoding algorithm has been widely used in the implementation of Low Density Parity Check (LDPC) decoders, due to its high convergence speed. However, the pipeline operation of the layered decoder may introduce memory access conflicts, which heavily deteriorates the decoder throughput. To essentially deal with the issue of memory access conflicts,
基金supported by the National Natural Science Foundation of China under Grants No.61172085,No.61103221,No.61133014,No.11061130539 and No.61021004
文摘This paper is concerned with (3,n) and (4,n) regular quasi-cyclic Low Density Parity Check (LDPC) code constructions from elementary number theory.Given the column weight,we determine the shift values of the circulant permutation matrices via arithmetic analysis.The proposed constructions of quasi-cyclic LDPC codes achieve the following main advantages simultaneously:1) our methods are constructive in the sense that we avoid any searching process;2) our methods ensure no four or six cycles in the bipartite graphs corresponding to the LDPC codes;3) our methods are direct constructions of quasi-cyclic LDPC codes which do not use any other quasi-cyclic LDPC codes of small length like component codes or any other algorithms/cyclic codes like building block;4)the computations of the parameters involved are based on elementary number theory,thus very simple and fast.Simulation results show that the constructed regular codes of high rates perform almost 1.25 dB above Shannon limit and have no error floor down to the bit-error rate of 10-6.
文摘In this paper, we present a Joint Source-Channel Decoding algorithm (JSCD) for Low-Density Parity Check (LDPC) codes by modifying the Sum-Product Algorithm (SPA) to account for the source redun-dancy, which results from the neighbouring Huffman coded bits. Simulations demonstrate that in the presence of source redundancy, the proposed algorithm gives better performance than the Separate Source and Channel Decoding algorithm (SSCD).
基金supported in part by the National Natural Science Foundation of China under Grant 61271262, 61473047 and 61572083Shaanxi Provincial Natural Science Foundation under Grant 2015JM6310the Special Fund for Basic Scientific Research of Central Colleges, Chang’an University under Grant 310824152010 and 00092014G1241043
文摘In order to guarantee reliable data transmission, powerful channel coding techniques are usually required in noncoherent ultra-wideband(UWB) communication systems. Accordingly, several forward error correction(FEC) codes, such as Reed-Solomon and convolutional codes have been used in noncoherent UWB systems to improve the bit error rate(BER) performance. In this paper, low-density parity-check(LDPC) codes are further studied as more powerful FEC candidates for noncoherent UWB systems. Two LDPC codes and the corresponding decoding procedures are presented for noncoherent UWB systems. Moreover, performance comparison between the LDPC codes and other FEC codes are provided for three major noncoherent UWB communication systems, namely, noncoherent pulse position modulation(NC-PPM), transmitted reference(TR) and transmitted reference pulse cluster(TRPC). Both theoretical analysis and simulation results show that the two investigated LDPC codes outperform other existing FEC codes with limited penalty in terms of complexity and therefore they are promising FEC candidates for noncoherent UWB systems with low-cost and low-power consumption.
文摘This paper describes an in-house developed language tool called VPerl used in developing a 250 MHz 32-bit high-performance low power embedded CPU core. The authors showed that use of this tool can compress the Verilog code by more than a factor of 5, increase the efficiency of the front-end design, reduce the bug rate significantly. This tool can be used to enhance the reusability of an intellectual property model, and facilitate porting design for different platforms.
文摘A low density parity check(LDPC)encoder with the codes of(8176,7154)and encoding rate of 7/8 under CCSDS standard for near space communication is designed.Based on LDPC encoding theory,the FPGA-based coding algorithm is designed.Based on the characteristics of LDPC generating matrix,the cyclic shift register is introduced as the core of the encoding circuit,and the shift-register-Adder-Accumulator(SRAA)structure is adopted to realize the fast calculation of matrix multiplication,so as to construct the encoding module with partial parallel encoding circuit as the core.In addition,the serial port input and output module,RAM storage module and control module are also designed,which together constitute the encoder system.The design scheme is implemented by FPGA hardware and verified by simulation and experiment.The results show that the test results of the designed LDPC encoder are consistent with the theoretical results.Therefore,the coding system is practical,and the design method is simple and efficient.
基金supported by the National Natural Science Foundation of China (No.41574137, 41304117)
文摘In this paper, based on the characteristics of polar codes, a new decode-and-forward strategy called generalized partial information relaying protocol is proposed for degraded multiple-relay networks with orthogonal receiver components(MRNORCs). In such a protocol, with the help of partial information from previous nodes, each relay node tries to recover the received source message and re-encodes part of the decoded message for transmission to satisfy the decoding requirements for the following relay node or the destination node. In order to construct practical polar codes, the nested structures are developed based on this protocol and the information sets corresponding to the partial messages forwarded are also calculated. The proposed scheme is proved to be capable of achieving the theoretical capacity of the degraded MRN-ORCs while still retains the low-complexity feature of polar codes. We perform simulations to testify the practicability of the proposed scheme and compare polar codes by using successive-cancellation list decoder(SCLD) with traditional low-density parity-check(LDPC) codes. The results show that the obtained polar codes provide significant gain.