An improved parallel weighted bit-flipping（PWBF） algorithm is presented. To accelerate the information exchanges between check nodes and variable nodes, the bit-flipping step and the check node updating step of the ...An improved parallel weighted bit-flipping（PWBF） algorithm is presented. To accelerate the information exchanges between check nodes and variable nodes, the bit-flipping step and the check node updating step of the original algorithm are parallelized. The simulation experiments demonstrate that the improved PWBF algorithm provides about 0. 1 to 0. 3 dB coding gain over the original PWBF algorithm. And the improved algorithm achieves a higher convergence rate. The choice of the threshold is also discussed, which is used to determine whether a bit should be flipped during each iteration. The appropriate threshold can ensure that most error bits be flipped, and keep the right ones untouched at the same time. The improvement is particularly effective for decoding quasi-cyclic low-density paritycheck（QC-LDPC） codes.展开更多
A hybrid decoding algorithm is proposed for nonbinary low-density parity-check （LDPC） codes, which combines the weighted symbol-flipping （WSF） algorithm with the fast Fourier trans- form q-ary sum-product algorit...A hybrid decoding algorithm is proposed for nonbinary low-density parity-check （LDPC） codes, which combines the weighted symbol-flipping （WSF） algorithm with the fast Fourier trans- form q-ary sum-product algorithm （FFT-QSPA）. The flipped position and value are determined by the symbol flipping metric and the received bit values in the first stage WSF algorithm. If the low- eomplexity WSF algorithm is failed, the second stage FFT-QSPA is activated as a switching strategy. Simulation results show that the proposed hybrid algorithm greatly reduces the computational complexity with the performance close to that of FFT-QSPA.展开更多
In this paper, an improved low-complexity sum-product decoding algorithm is presented for low-density parity-check （LDPC） codes. In the proposed algorithm, reduction in computational complexity is achieved by utiliz...In this paper, an improved low-complexity sum-product decoding algorithm is presented for low-density parity-check （LDPC） codes. In the proposed algorithm, reduction in computational complexity is achieved by utilizing fast Fourier transform （FFT） with time shift in the check node process. The improvement in the decoding performance is achieved by utilizing an op- timized integer constant in the variable node process. Simulation results show that the proposed algorithm achieves an overall coding gain improvement ranging from 0.04 to 0.46 dB. Moreover, when compared with the sum-product algorithm （SPA）, the proposed decoding algorithm can achieve a reduction of 42%-67% of the total number of arithmetic operations required for the decoding process.展开更多
基金The National High Technology Research and Development Program of China (863Program) ( No2009AA01Z235,2006AA01Z263)the Research Fund of the National Mobile Communications Research Laboratory of Southeast University(No2008A10)
文摘An improved parallel weighted bit-flipping（PWBF） algorithm is presented. To accelerate the information exchanges between check nodes and variable nodes, the bit-flipping step and the check node updating step of the original algorithm are parallelized. The simulation experiments demonstrate that the improved PWBF algorithm provides about 0. 1 to 0. 3 dB coding gain over the original PWBF algorithm. And the improved algorithm achieves a higher convergence rate. The choice of the threshold is also discussed, which is used to determine whether a bit should be flipped during each iteration. The appropriate threshold can ensure that most error bits be flipped, and keep the right ones untouched at the same time. The improvement is particularly effective for decoding quasi-cyclic low-density paritycheck（QC-LDPC） codes.
基金Supported by the National High Technology Research and Development Programme of China(No.2009AAJ128,2009AAJ208,2010AA7010422)
文摘A hybrid decoding algorithm is proposed for nonbinary low-density parity-check （LDPC） codes, which combines the weighted symbol-flipping （WSF） algorithm with the fast Fourier trans- form q-ary sum-product algorithm （FFT-QSPA）. The flipped position and value are determined by the symbol flipping metric and the received bit values in the first stage WSF algorithm. If the low- eomplexity WSF algorithm is failed, the second stage FFT-QSPA is activated as a switching strategy. Simulation results show that the proposed hybrid algorithm greatly reduces the computational complexity with the performance close to that of FFT-QSPA.
文摘In this paper, an improved low-complexity sum-product decoding algorithm is presented for low-density parity-check （LDPC） codes. In the proposed algorithm, reduction in computational complexity is achieved by utilizing fast Fourier transform （FFT） with time shift in the check node process. The improvement in the decoding performance is achieved by utilizing an op- timized integer constant in the variable node process. Simulation results show that the proposed algorithm achieves an overall coding gain improvement ranging from 0.04 to 0.46 dB. Moreover, when compared with the sum-product algorithm （SPA）, the proposed decoding algorithm can achieve a reduction of 42%-67% of the total number of arithmetic operations required for the decoding process.
