Derived from a proposed universal mathematical expression, this paper investigates a novel algo-rithm for parallel Cyclic Redundancy Check (CRC) computation, which is an iterative algorithm to update the check-bit seq...Derived from a proposed universal mathematical expression, this paper investigates a novel algo-rithm for parallel Cyclic Redundancy Check (CRC) computation, which is an iterative algorithm to update the check-bit sequence step by step and suits to various argument selections of CRC computation. The algorithm proposed is quite suitable for hardware implementation. The simulation implementation and performance analysis suggest that it could efficiently speed up the computation compared with the conventional ones. The algorithm is implemented in hardware at as high as 21Gbps, and its usefulness in high-speed CRC computa-tions is implied, such as Asynchronous Transfer Mode (ATM) networks and 10G Ethernet.展开更多
This paper presents a CRC (Cyclic Redundancy Check)-aided turbo equalization approach to reduce the computational complexity. In this approach,CRC code bits are padded to the end of each transmit block,and a cyclic re...This paper presents a CRC (Cyclic Redundancy Check)-aided turbo equalization approach to reduce the computational complexity. In this approach,CRC code bits are padded to the end of each transmit block,and a cyclic redundancy check is performed after decoding each block at the receiver end. If the check sum is zero,which means the receive block is correct,the corresponding LLRs (Log Likelihood Ratios) of this block are set high reliable values,and all the computations corresponding to this block can be cancelled for the subsequent outer iterations. With a lower computational complexity the proposed approach can achieve the same as or even better performance than the conventional non-CRC method.展开更多
基金Supported by the National Natural Science Foundation of China (No.60172029) and the Natural Science Foun-dation of Shaanxi Province (No.2004F04).
文摘Derived from a proposed universal mathematical expression, this paper investigates a novel algo-rithm for parallel Cyclic Redundancy Check (CRC) computation, which is an iterative algorithm to update the check-bit sequence step by step and suits to various argument selections of CRC computation. The algorithm proposed is quite suitable for hardware implementation. The simulation implementation and performance analysis suggest that it could efficiently speed up the computation compared with the conventional ones. The algorithm is implemented in hardware at as high as 21Gbps, and its usefulness in high-speed CRC computa-tions is implied, such as Asynchronous Transfer Mode (ATM) networks and 10G Ethernet.
基金Supported in part by the National Natural Science Foundation of China (No.60496311).
文摘This paper presents a CRC (Cyclic Redundancy Check)-aided turbo equalization approach to reduce the computational complexity. In this approach,CRC code bits are padded to the end of each transmit block,and a cyclic redundancy check is performed after decoding each block at the receiver end. If the check sum is zero,which means the receive block is correct,the corresponding LLRs (Log Likelihood Ratios) of this block are set high reliable values,and all the computations corresponding to this block can be cancelled for the subsequent outer iterations. With a lower computational complexity the proposed approach can achieve the same as or even better performance than the conventional non-CRC method.
