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基于Booth编码模乘模块RSA的VLSI设计 被引量:2
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作者 舒妍 卢君明 《西安电子科技大学学报》 EI CAS CSCD 北大核心 2002年第3期363-367,共5页
在Montgomery模乘算法基础上 ,采用大数乘法器常用的Booth编码技术缩减Montgomery模乘法的中间运算过程 ,将算法迭代次数减为原来的一半 .同时采用省进位加法器作为大数加法的核心 ,使模乘算法中一次迭代的延迟为两个一位全加器的延迟 ... 在Montgomery模乘算法基础上 ,采用大数乘法器常用的Booth编码技术缩减Montgomery模乘法的中间运算过程 ,将算法迭代次数减为原来的一半 .同时采用省进位加法器作为大数加法的核心 ,使模乘算法中一次迭代的延迟为两个一位全加器的延迟 ,提高了处理器的时钟频率 .在 0 2 5 μm工艺下 ,对于10 2 4位操作数 ,可在 2 0 0MHz时钟频率下工作 ,其加密速率约为 178kbit/s . 展开更多
关键词 BOOTH编码 RSA VLSI设计 模幂乘法 乘算法 因特网 安全
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The RSA Cryptoprocessor Hardware Implementation Based on Modified Montgomery Algorithm 被引量:2
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作者 陈波 王旭 戎蒙恬 《Journal of Shanghai Jiaotong university(Science)》 EI 2005年第2期107-111,共5页
RSA(Rivest-Shamir-Adleman)public-key cryptosystem is widely used in the information security area such as encryption and digital signature. Based on the modified Montgomery modular multiplication algorithm, a new arch... RSA(Rivest-Shamir-Adleman)public-key cryptosystem is widely used in the information security area such as encryption and digital signature. Based on the modified Montgomery modular multiplication algorithm, a new architecture using CSA(carry save adder)was presented to implement modular multiplication. Compared with the popular modular multiplication algorithms using two CSA, the presented algorithm uses only one CSA, so it can improve the time efficiency of RSA cryptoprocessor and save about half of hardware resources for modular multiplication. With the increase of encryption data size n, the clock cycles for the encryption procedure reduce in (T(n^2),) compared with the modular multiplication algorithms using two CSA. 展开更多
关键词 Montgomery algorithm modular multiplication modular exponentiation
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FPGA IMPLEMENTATION OF RSA PUBLIC-KEY CRYPTOGRAPHIC COPROCESSOR BASED ON SYSTOLIC LINEAR ARRAY ARCHITECTURE 被引量:2
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作者 Wen Nuan Dai Zibin Zhang Yongfu 《Journal of Electronics(China)》 2006年第5期718-722,共5页
In order to make the typical Montgomery’s algorithm suitable for implementation on FPGA, a modified version is proposed and then a high-performance systolic linear array architecture is designed for RSA cryptosystem ... In order to make the typical Montgomery’s algorithm suitable for implementation on FPGA, a modified version is proposed and then a high-performance systolic linear array architecture is designed for RSA cryptosystem on the basis of the optimized algorithm. The proposed systolic array architecture has dis- tinctive features, i.e. not only the computation speed is significantly fast but also the hardware overhead is drastically decreased. As a major practical result, the paper shows that it is possible to implement public-key cryptosystem at secure bit lengths on a single commercially available FPGA. 展开更多
关键词 RSA Montgomery's algorithm Systolic linear array Modular multiplication Modular exponentiation
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