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基于数字电路对模拟信号的转化研究
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作者 张琦 《科技创新导报》 2019年第6期4-4,6,共2页
以数字为基础的电路就是数字电路,而数字电路所使用的数字就是"0"和"1",因此数字电路通常都比较简单,而其所发出的模拟信号也是由"0"和"1"所组成的。而要将模拟信号转化为数字信号,就需要通过... 以数字为基础的电路就是数字电路,而数字电路所使用的数字就是"0"和"1",因此数字电路通常都比较简单,而其所发出的模拟信号也是由"0"和"1"所组成的。而要将模拟信号转化为数字信号,就需要通过设计不同逻辑电路才可以达成这一点。所以,就有必要研究数字电路对模拟信号的转化。因此,本文首先将概述模拟电路放大器,然后分析数字电路对模拟信号的放大,最后详细阐述数字信号在人们日常生活中的具体应用,希望可以为相关工作人员提供有用的参考。 展开更多
关键词 数字电路 模拟信号 模拟电路放大器 信号转化
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Rail-to-rail op-amp with constant transconductance,SR and gain
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作者 常昌远 李弦 +1 位作者 姚建楠 李娟 《Journal of Southeast University(English Edition)》 EI CAS 2008年第2期163-167,共5页
A novel general-purpose low-voltage rail-to-rail CMOS ( complementary metal-oxide-semiconductor transistor ) operational amplifier (op-amp)is introduced, which obtains constant transconductance, slew rate and cons... A novel general-purpose low-voltage rail-to-rail CMOS ( complementary metal-oxide-semiconductor transistor ) operational amplifier (op-amp)is introduced, which obtains constant transconductance, slew rate and constant high gain over the entire input common mode voltage range. The proposed scheme has the potential for applications in deep submicrometer technology, as the operation of the circuit does not exclusively rely on the square-law or the linear-law of transistors. The scheme is compact and suitable for applications as VLSI cell. The rail-to- rail op-amp has been implemented in DPDM 0. 6 μm mixedsignal process. The simulations show that in the entire range of input common mode voltage, the variations in transconductance, SR and gain are 1%, 2. 3%, 1.36 dB, respectively. Based on this, the layout and tape-out are carded out. The area of layout is 0. 072 mm^2. The test results are basically consistent with the circuit simulation. 展开更多
关键词 CMOS analog circuit op-amp RAIL-TO-RAIL constant transconductance constant slew rate constant gain
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A 3V 5.88mW 13b 400kHz Sigma-Delta Modulator with 84dB Dynamic Range
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作者 李卓 杨华中 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2008年第11期2232-2237,共6页
This paper introduces a high-revolution,200kHz signal bandwidth EA modulator for low-IF GSM receivers that adopts a 2-1 cascaded single-bit structure to achieve high linearity and stability. Our design is realized in ... This paper introduces a high-revolution,200kHz signal bandwidth EA modulator for low-IF GSM receivers that adopts a 2-1 cascaded single-bit structure to achieve high linearity and stability. Our design is realized in a standard 0.18μm CMOS process with art active area of 0.5mm× 1.1mm.The EA modulator is driven by a single 19.2MHz clock signal and dissipates 5.88mW from 3V power supply. The experimental results show that,with an oversampling ratio of 48, the modulator achieves a 84.4dB dynamic range,73.8dB peak SNDR, and 80dB peak SNR in the signal bandwidth of 200kHz. 展开更多
关键词 cascaded sigma-delta modulator analog-digital converter switched-capacitor circuits operational amplifiers CMOS analog integrated circuits
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