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计算机模拟运算器软件的设计
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作者 戴学松 《中国教育技术装备》 2003年第9期4-4,6,共2页
介绍了计算机组成原理辅助教学软件的设计思想和主要教学功能.
关键词 计算机组成原理 教学软件 计算机辅助教学 模拟运算器
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8279芯片与模拟运算器
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作者 果晓来 周宁 《微型机与应用》 1995年第9期13-14,共2页
用8279与8031的接口电路实现模拟运算器功能.
关键词 键盘显示器件 8279芯片 模拟运算器 运算器
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Fully Differential Leapfrog Implementation for High-Pass Ladder Filters
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作者 鲍虎 张海丹 +1 位作者 史庆伟 滕建辅 《Transactions of Tianjin University》 EI CAS 2010年第2期114-117,共4页
This paper presents a novel leapfrog signal flow graph (SFG) implementation by fully differential Op amp integrators, which combines low sensitivity, high dynamic range with simple circuit configuration. The direct ... This paper presents a novel leapfrog signal flow graph (SFG) implementation by fully differential Op amp integrators, which combines low sensitivity, high dynamic range with simple circuit configuration. The direct SFG simulation and leapfrog SFG simulation can yield integrator-based structures likewise, but both of them will lead to higher circuit complexity, noise density and sensitivity. Three Butterworth 5-order high-pass filters with a pass band edge frequency of 1.778 kHz are designed based on different SFGs. From the example, the noise density of the sim- plest leapfrog configuration is approximately 0.4 nV/Hz~/2 lower than those of the other two in the stop band, and shows the best noise density in the pass band. The sensitivity densities of two types of leapfrog filters are approxi- mately equivalent, while that of the direct SFG simulation filter is much higher. However, the pass band response of the simplest configuration is not as good as those of the other two because of two parasitic zeros (at 708 kHz, -31.6 dB and 1.59 MHz, 20.55 dB) and a parasitic pole (at 4.57 MHz, 45.5 dB). 展开更多
关键词 active filter analog circuit integrated circuit
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A 3V 5.88mW 13b 400kHz Sigma-Delta Modulator with 84dB Dynamic Range
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作者 李卓 杨华中 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2008年第11期2232-2237,共6页
This paper introduces a high-revolution,200kHz signal bandwidth EA modulator for low-IF GSM receivers that adopts a 2-1 cascaded single-bit structure to achieve high linearity and stability. Our design is realized in ... This paper introduces a high-revolution,200kHz signal bandwidth EA modulator for low-IF GSM receivers that adopts a 2-1 cascaded single-bit structure to achieve high linearity and stability. Our design is realized in a standard 0.18μm CMOS process with art active area of 0.5mm× 1.1mm.The EA modulator is driven by a single 19.2MHz clock signal and dissipates 5.88mW from 3V power supply. The experimental results show that,with an oversampling ratio of 48, the modulator achieves a 84.4dB dynamic range,73.8dB peak SNDR, and 80dB peak SNR in the signal bandwidth of 200kHz. 展开更多
关键词 cascaded sigma-delta modulator analog-digital converter switched-capacitor circuits operational amplifiers CMOS analog integrated circuits
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