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AD7714可编程模数转换器及其应用 被引量:2
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作者 秦泓江 肖圣 +1 位作者 高世博 郑福荣 《石油仪器》 2005年第4期37-38,90-91,共2页
井下仪器的特殊性给嵌入式仪器的设计提出了很高要求。AD7714是一种直接从传感器接收电信号,放大系数可编程,低功耗的低频A/D转换器,转换精度为24位,选择此片可有效简化硬件电路结构,提高仪器的性价比。
关键词 嵌入式 sigma—deha技术 可编程模数转换器
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精确频率输出的超低时延DDS电路设计 被引量:6
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作者 王国洪 宛强 +1 位作者 姚亚峰 钟梁 《哈尔滨工业大学学报》 EI CAS CSCD 北大核心 2019年第5期44-49,共6页
使用CMOS工艺设计高性能、低成本的直接数字频率合成器DDS是一项十分具有挑战性的任务.本文提出了一种模数可编程的超低时延DDS电路设计.通过增加一个辅助相位累加器,可以根据输出频率的需要来设置辅助相位累加器的输入和模数配置来产... 使用CMOS工艺设计高性能、低成本的直接数字频率合成器DDS是一项十分具有挑战性的任务.本文提出了一种模数可编程的超低时延DDS电路设计.通过增加一个辅助相位累加器,可以根据输出频率的需要来设置辅助相位累加器的输入和模数配置来产生小数复合频率控制字,从而可以进行各种频率的精确输出,完全消除了输出频率误差.还针对CORDIC算法进行了优化改进,提出了一种仅需要小容量的查找表和简单角度校正的CORDIC实现方法,免除了迭代运算过程,设计了一种超低时延的相位幅度转换电路.在电路资源消耗没有增加的前提下,设计电路不仅实现了精确频率输出,还大大降低了电路的输出时延.验证结果表明:本DDS设计电路输出频率不存在频率误差,并且只需要两个时钟周期就能得到高精度的正余弦波输出.本设计通过对相位累加器和相位幅度转换电路的改进,消除了输出频率误差和降低了输出时延,具有输出频率精确、输出时延小、成本低等优点,更加适合输出频率精度要求高、实时性强的信号处理应用场合. 展开更多
关键词 模数可编程 相位幅度变换 坐标旋转数字计算 直接数字频率合成 数字电路设计
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Design of Parallel Electrical Resistance Tomography System for Measuring Multiphase Flow 被引量:3
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作者 董峰 许聪 +1 位作者 张志强 任尚杰 《Chinese Journal of Chemical Engineering》 SCIE EI CAS CSCD 2012年第2期368-379,共12页
ERT(electrical resistance tomography) is effective method for visualization of multiphase flows,offering some advantages of rapid response and low cost,so as to explore the transient hydrodynamics.Aiming at this targe... ERT(electrical resistance tomography) is effective method for visualization of multiphase flows,offering some advantages of rapid response and low cost,so as to explore the transient hydrodynamics.Aiming at this target,a fully programmable and reconfigurable FPGA(field programmable gate array)-based Compact PCI(peripheral component interconnect) bus linked sixteen-channel ERT system has been presented.The data acquisition system is carefully designed with function modules of signal generator module;Compact PCI transmission module and data processing module(including data sampling,filtering and demodulating).The processing module incorporates a powerful FPGA with Compact PCI bus for communication,and the measurement process management is conducted in FPGA.Image reconstruction algorithms with different speed and accuracy are also coded for this system.The system has been demonstrated in real time(1400 frames per second for 50 kHz excitation) with signal-noise-ratio above 62 dB and repeatability error below 0.7%.Static experiments have been conducted and the images manifested good resolution relative to the actual object distribution.The parallel ERT system has provided alternative experimental platform for the multiphase flow measurements by the dynamic experiments in terms of concentration and velocity. 展开更多
关键词 electrical resistance tomography data acquisition compact peripheral component interconnect field programmable gate array digital filter digital demodulation
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High-resolution data acquisition technique in broadband seismic observation systems 被引量:5
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作者 GAO Shang Hua XUE Bing +3 位作者 LI Jiang LIN Zhan CHEN Yang ZHU Xiao Yi 《Science China(Technological Sciences)》 SCIE EI CAS CSCD 2016年第6期961-972,共12页
The dynamic range of the currently most widely used 24-bit seismic data acquisition devices is 10–20 d B lower than that of broadband seismometers, and this can affect the completeness of seismic waveform recordings ... The dynamic range of the currently most widely used 24-bit seismic data acquisition devices is 10–20 d B lower than that of broadband seismometers, and this can affect the completeness of seismic waveform recordings under certain conditions. However, this problem is not easy to solve because of the lack of analog to digital converter(ADC) chips with more than 24 bits in the market. In this paper, we propose a method in which an adder, an integrator, a digital to analog converter chip, a field-programmable gate array, and an existing low-resolution ADC chip are used to build a third-order 16-bit oversampling delta-sigma modulator. This modulator is equipped with a digital decimation filter, thus facilitating higher resolution and larger dynamic range seismic data acquisition. Experimental results show that, within the 0.1–40 Hz frequency range, the circuit board's dynamic range reaches 158.2 d B, its resolution reaches 25.99 bits, and its linearity error is below 2.5 ppm, which is better than what is achieved by the commercial 24-bit ADC chips ADS1281 and CS5371. This demonstrates that the proposed method may alleviate or even completely resolve the amplitude-limitation problem that so commonly occurs with broadband observation instruments during strong earthquakes. 展开更多
关键词 seismic data acquisition analog to digital conversion (ADC) high resolution dynamic range delta-sigma modulation
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