采用开顶式气室(Open Top Chambers)进行水培试验,以两种氮效率玉米(ZeamaysL.)基因型为供试作物,通过不同大气NH3浓度处理,测定苗期各叶绿素荧光动力学参数。结果表明,供氮介质和大气NH3浓度升高对两种氮效率玉米基因型的初始荧光值(Fo...采用开顶式气室(Open Top Chambers)进行水培试验,以两种氮效率玉米(ZeamaysL.)基因型为供试作物,通过不同大气NH3浓度处理,测定苗期各叶绿素荧光动力学参数。结果表明,供氮介质和大气NH3浓度升高对两种氮效率玉米基因型的初始荧光值(Fo)不存在显著影响。高供氮介质下,在NH3浓度升高时,氮高效5号基因型的最大荧光产量(Fm)和可变荧光(Fv)均显著减小(p<0.05),而氮低效基因型四单19的Fm、Fv值显著增加;低供氮介质下,大气NH3浓度升高对2种基因型Fm、Fv值的影响结果与高供氮介质时相反。说明大气NH3浓度升高对生长在高供氮介质下的氮高效5号基因型有一定的抑制作用,而对氮低效基因型四单19有一定程度的促进作用。在不同供氮介质下,大气NH3浓度升高时,两种氮效率玉米基因型的qN、qP值减小,说明大气NH3浓度升高时,作物对光合机构的保护能力比大气背景NH3浓度时弱。展开更多
A high performance 70nm CMOS device has been demonstrated for the first time in the continent, China. Some innovations in techniques are applied to restrain the short channel effect and improve the driving ability, ...A high performance 70nm CMOS device has been demonstrated for the first time in the continent, China. Some innovations in techniques are applied to restrain the short channel effect and improve the driving ability, such as 3nm nitrided oxide, dual poly Si gate electrode, novel super steep retrograde channel doping by heavy ion implantation, ultra shallow S/D extension formed by Ge PAI(Pre Amorphism Implantation) plus LEI(Low Energy Implantation), thin and low resistance Ti SALICIDE by Ge PAI and special cleaning, etc. The shortest channel length of the CMOS device is 70nm. The threshold voltages, G m and off current are 0 28V,490mS·mm -1 and 0 08nA/μm for NMOS and -0 3V,340mS·mm -1 and 0 2nA/μm for PMOS, respectively. Delays of 23 5ps/stage at 1 5V, 17 5ps/stage at 2 0V and 12 5ps/stage at 3V are achieved in the 57 stage unloaded 100nm CMOS ring oscillator circuits.展开更多
On December 17,2015,the Beijing Institute of Structural and Environmental Engineering and the Beijing Institute of Aerospace Testing Technology successfully conducted a liquid nitrogen medium destructive test of LM-5 ...On December 17,2015,the Beijing Institute of Structural and Environmental Engineering and the Beijing Institute of Aerospace Testing Technology successfully conducted a liquid nitrogen medium destructive test of LM-5 first stage hydrogen tank,marking the completion of the ground static tests for LM-5 tanks.展开更多
Nitrogen implantation in silicon substrate at fixed energy of 35keV and split dose of 10 14～5×10 14cm -2 is performed before gate oxidation.The experiment results indicate that with the increasing of implanta...Nitrogen implantation in silicon substrate at fixed energy of 35keV and split dose of 10 14～5×10 14cm -2 is performed before gate oxidation.The experiment results indicate that with the increasing of implantation dose of nitrogen,oxidation rate of gate decreases.The retardation in oxide growth is weakened due to thermal annealing after nitrogen implantation.After nitrogen is implanted at the dose of 2×10 14cm -2,initial O 2 injection method which is composed of an O 2 injection/N 2 annealing/main oxidation,is applied for preparation of 3 4nm gate oxide.Compared with the control process,which is composed of N 2 annealing/main oxidation,initial O 2 injection process suppresses leakage current of the gate oxide.But Q bd and HF C-V characteristics are almost identical for the samples fabricated by two different oxidation processes.展开更多
By complementing the equivalent oxide thickness （EOT） of a 1.7nm nitride/oxynitride （N/O） stack gate dielectric （EOT- 1.7nm） with a W/TiN metal gate electrode,metal gate CMOS devices with sub-100nm gate length a...By complementing the equivalent oxide thickness （EOT） of a 1.7nm nitride/oxynitride （N/O） stack gate dielectric （EOT- 1.7nm） with a W/TiN metal gate electrode,metal gate CMOS devices with sub-100nm gate length are fabricated in China for the first time. The key technologies adopted to restrain SCE and to improve drive ability include a 1.7nm N/O stack gate dielectric, non-CMP planarization technology, a T-type refractory W/TiN metal stack gate electrode, and a novel super steep retrograde channel doping using heavy ion implantation and a double sidewall scheme. Using these optimized key technologies, high performance 95nm metal gate CMOS devices with excellent SCE and good driving ability are fabricated. Under power supply voltages of VDS ± 1.5V and VGS± 1.8V,drive currents of 679μA/μm for nMOS and - 327μA/μm for pMOS are obtained. A subthreshold slope of 84.46mV/dec, DIBL of 34.76mV/V, and Vth of 0.26V for nMOS, and a subthreshold slope of 107.4mV/dec,DIBL of 54.46mV/V, and Vth of 0.27V for pMOS are achieved. These results show that the combined technology has indeed thoroughly eliminated the boron penetration phenomenon and polysilicon depletion effect ,effectively reduced gate tunneling leakage, and improved device reliability.展开更多
Electrical properties of high quality ultra thin nitride/oxynitride(N/O)stack dielectrics pMOS capacitor with refractory metal gate electrode are investigated,and ultra thin (<2 nm) N/O stack gate dielectrics with ...Electrical properties of high quality ultra thin nitride/oxynitride(N/O)stack dielectrics pMOS capacitor with refractory metal gate electrode are investigated,and ultra thin (<2 nm) N/O stack gate dielectrics with significant low leakage current and high resistance to boron penetration are fabricated.Experiment results show that the stack gate dielectric of nitride/oxynitride combined with improved sputtered tungsten/titanium nitride (W/TiN) gate electrode is one of the candidates for deep sub-micron metal gate CMOS devices.展开更多
文摘采用开顶式气室(Open Top Chambers)进行水培试验,以两种氮效率玉米(ZeamaysL.)基因型为供试作物,通过不同大气NH3浓度处理,测定苗期各叶绿素荧光动力学参数。结果表明,供氮介质和大气NH3浓度升高对两种氮效率玉米基因型的初始荧光值(Fo)不存在显著影响。高供氮介质下,在NH3浓度升高时,氮高效5号基因型的最大荧光产量(Fm)和可变荧光(Fv)均显著减小(p<0.05),而氮低效基因型四单19的Fm、Fv值显著增加;低供氮介质下,大气NH3浓度升高对2种基因型Fm、Fv值的影响结果与高供氮介质时相反。说明大气NH3浓度升高对生长在高供氮介质下的氮高效5号基因型有一定的抑制作用,而对氮低效基因型四单19有一定程度的促进作用。在不同供氮介质下,大气NH3浓度升高时,两种氮效率玉米基因型的qN、qP值减小,说明大气NH3浓度升高时,作物对光合机构的保护能力比大气背景NH3浓度时弱。
文摘A high performance 70nm CMOS device has been demonstrated for the first time in the continent, China. Some innovations in techniques are applied to restrain the short channel effect and improve the driving ability, such as 3nm nitrided oxide, dual poly Si gate electrode, novel super steep retrograde channel doping by heavy ion implantation, ultra shallow S/D extension formed by Ge PAI(Pre Amorphism Implantation) plus LEI(Low Energy Implantation), thin and low resistance Ti SALICIDE by Ge PAI and special cleaning, etc. The shortest channel length of the CMOS device is 70nm. The threshold voltages, G m and off current are 0 28V,490mS·mm -1 and 0 08nA/μm for NMOS and -0 3V,340mS·mm -1 and 0 2nA/μm for PMOS, respectively. Delays of 23 5ps/stage at 1 5V, 17 5ps/stage at 2 0V and 12 5ps/stage at 3V are achieved in the 57 stage unloaded 100nm CMOS ring oscillator circuits.
文摘On December 17,2015,the Beijing Institute of Structural and Environmental Engineering and the Beijing Institute of Aerospace Testing Technology successfully conducted a liquid nitrogen medium destructive test of LM-5 first stage hydrogen tank,marking the completion of the ground static tests for LM-5 tanks.
文摘Nitrogen implantation in silicon substrate at fixed energy of 35keV and split dose of 10 14～5×10 14cm -2 is performed before gate oxidation.The experiment results indicate that with the increasing of implantation dose of nitrogen,oxidation rate of gate decreases.The retardation in oxide growth is weakened due to thermal annealing after nitrogen implantation.After nitrogen is implanted at the dose of 2×10 14cm -2,initial O 2 injection method which is composed of an O 2 injection/N 2 annealing/main oxidation,is applied for preparation of 3 4nm gate oxide.Compared with the control process,which is composed of N 2 annealing/main oxidation,initial O 2 injection process suppresses leakage current of the gate oxide.But Q bd and HF C-V characteristics are almost identical for the samples fabricated by two different oxidation processes.
文摘By complementing the equivalent oxide thickness （EOT） of a 1.7nm nitride/oxynitride （N/O） stack gate dielectric （EOT- 1.7nm） with a W/TiN metal gate electrode,metal gate CMOS devices with sub-100nm gate length are fabricated in China for the first time. The key technologies adopted to restrain SCE and to improve drive ability include a 1.7nm N/O stack gate dielectric, non-CMP planarization technology, a T-type refractory W/TiN metal stack gate electrode, and a novel super steep retrograde channel doping using heavy ion implantation and a double sidewall scheme. Using these optimized key technologies, high performance 95nm metal gate CMOS devices with excellent SCE and good driving ability are fabricated. Under power supply voltages of VDS ± 1.5V and VGS± 1.8V,drive currents of 679μA/μm for nMOS and - 327μA/μm for pMOS are obtained. A subthreshold slope of 84.46mV/dec, DIBL of 34.76mV/V, and Vth of 0.26V for nMOS, and a subthreshold slope of 107.4mV/dec,DIBL of 54.46mV/V, and Vth of 0.27V for pMOS are achieved. These results show that the combined technology has indeed thoroughly eliminated the boron penetration phenomenon and polysilicon depletion effect ,effectively reduced gate tunneling leakage, and improved device reliability.
文摘Electrical properties of high quality ultra thin nitride/oxynitride(N/O)stack dielectrics pMOS capacitor with refractory metal gate electrode are investigated,and ultra thin (<2 nm) N/O stack gate dielectrics with significant low leakage current and high resistance to boron penetration are fabricated.Experiment results show that the stack gate dielectric of nitride/oxynitride combined with improved sputtered tungsten/titanium nitride (W/TiN) gate electrode is one of the candidates for deep sub-micron metal gate CMOS devices.
