提出一种基于TSMC40LP工艺的输入信号缓冲器,用于12 bit 4 GSPS ADC的缓冲器设计。本缓冲器采用开环源随器结构,由于工艺角和温度变化,开环结构的缓冲器的输出共模将会漂移,导致比较器的输入共模发生漂移,使得比较器的比较结果发生错误...提出一种基于TSMC40LP工艺的输入信号缓冲器,用于12 bit 4 GSPS ADC的缓冲器设计。本缓冲器采用开环源随器结构,由于工艺角和温度变化,开环结构的缓冲器的输出共模将会漂移,导致比较器的输入共模发生漂移,使得比较器的比较结果发生错误。采用Replica共模反馈的方式为主缓冲器提供共模,实现缓冲器的输出共模的稳定,避免比较器因为共模变化而工作不正常。为了达到线性度的要求,通过叠层源随器和电容,将输入信号耦合到源随器的漏端,避免了短沟道器件的沟调效应。源随器采用深N阱器件,消除了衬底偏置效应。本源随器提供强大的输入信号驱动,避免多通道ADC交织时,相互之间的影响。同时驱动大的电容负载,并提供高质量的输入信号。后仿真得到源随器的最小带宽为9.7 GHz,在1 pF负载,500 MHz,800 mVpp输入信号时,SFDR为79.86 d B,满足12 bit 4 GSPS ADC的要求。展开更多
Metal-oxide-semiconductor field effect transistor(MOSFET) intrinsic gain degradation caused by channel length modulation(CLM) effect is examined.A simplified model based on Berkeley short-channel insulator-gate field ...Metal-oxide-semiconductor field effect transistor(MOSFET) intrinsic gain degradation caused by channel length modulation(CLM) effect is examined.A simplified model based on Berkeley short-channel insulator-gate field effect transistor model version 4(BSIM4) current expression for sub-100 nm MOSFET intrinsic gain is deduced,which only needs a few technology parameters.With this transistor intrinsic gain model,complementary metal-oxide-semiconductor(CMOS) operational amplifier(op amp) DC gain could be predicted.A two-stage folded cascode op amp is used as an example in this work.Non-minimum length device is used to improve the op amp DC gain.An improvement of 20 dB is proved when using doubled channel length design.Optimizing transistor bias condition and using advanced technology with thinner gate dielectric thickness and shallower source/drain junction depth can also increase the op amp DC gain.After these,a full op amp DC gain scaling roadmap is proposed,from 130 nm technology node to 32 nm technology node.Five scaled op amps are built and their DC gains in simulation roll down from 69.6 to 41.1 dB.Simulation shows transistors biased at higher source-drain voltage will have more impact on the op amp DC gain scaling over technology.The prediction based on our simplified gain model agrees with SPICE simulation results.展开更多
文摘提出一种基于TSMC40LP工艺的输入信号缓冲器,用于12 bit 4 GSPS ADC的缓冲器设计。本缓冲器采用开环源随器结构,由于工艺角和温度变化,开环结构的缓冲器的输出共模将会漂移,导致比较器的输入共模发生漂移,使得比较器的比较结果发生错误。采用Replica共模反馈的方式为主缓冲器提供共模,实现缓冲器的输出共模的稳定,避免比较器因为共模变化而工作不正常。为了达到线性度的要求,通过叠层源随器和电容,将输入信号耦合到源随器的漏端,避免了短沟道器件的沟调效应。源随器采用深N阱器件,消除了衬底偏置效应。本源随器提供强大的输入信号驱动,避免多通道ADC交织时,相互之间的影响。同时驱动大的电容负载,并提供高质量的输入信号。后仿真得到源随器的最小带宽为9.7 GHz,在1 pF负载,500 MHz,800 mVpp输入信号时,SFDR为79.86 d B,满足12 bit 4 GSPS ADC的要求。
文摘Metal-oxide-semiconductor field effect transistor(MOSFET) intrinsic gain degradation caused by channel length modulation(CLM) effect is examined.A simplified model based on Berkeley short-channel insulator-gate field effect transistor model version 4(BSIM4) current expression for sub-100 nm MOSFET intrinsic gain is deduced,which only needs a few technology parameters.With this transistor intrinsic gain model,complementary metal-oxide-semiconductor(CMOS) operational amplifier(op amp) DC gain could be predicted.A two-stage folded cascode op amp is used as an example in this work.Non-minimum length device is used to improve the op amp DC gain.An improvement of 20 dB is proved when using doubled channel length design.Optimizing transistor bias condition and using advanced technology with thinner gate dielectric thickness and shallower source/drain junction depth can also increase the op amp DC gain.After these,a full op amp DC gain scaling roadmap is proposed,from 130 nm technology node to 32 nm technology node.Five scaled op amps are built and their DC gains in simulation roll down from 69.6 to 41.1 dB.Simulation shows transistors biased at higher source-drain voltage will have more impact on the op amp DC gain scaling over technology.The prediction based on our simplified gain model agrees with SPICE simulation results.
