A 1.8V 8b 125Msample/s pipelined A/D converter is presented.Power efficiency is optimized by size scaling down scheme using low power single stage cascode amplifier with a gain boosted structure.Global clock tree and ...A 1.8V 8b 125Msample/s pipelined A/D converter is presented.Power efficiency is optimized by size scaling down scheme using low power single stage cascode amplifier with a gain boosted structure.Global clock tree and local generators are employed to avoid loss and overlap of clock period.The ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 49.5dB(7.9ENOB) for an input of 62MHz at full speed of 125MHz,consuming only 71mW.It is implemented in 0.18μm CMOS technology with a core area of 0.45mm 2.展开更多
A complementary metal-oxide-semiconductor transistor （CMOS） voltage-to-current（VTC）converter with high linearity for current-mode analog and digital integrated circuits is described. A high gain operational amplif...A complementary metal-oxide-semiconductor transistor （CMOS） voltage-to-current（VTC）converter with high linearity for current-mode analog and digital integrated circuits is described. A high gain operational amplifier （OPA） is utilized to form negative feedback. A proportional to absolute temperature （PTAT） current reference with transistors operated in a weak inversion is used as the bias circuit. The resistor and the OPA nonlinearity behavior are analyzed in detail. By optimizing parameters in OPA and adopting a small voltage coefficient polysilicon resistor as a linear device, a high linearity is achieved. The circuit is implemented in a standard 0. 6 μm CMOS technology. The low frequency gain of the OPA exceeds 90 dB. The test results indicate that the total harmonic distortion （THD）is 0. 000 2%. The common-mode input linearity range is 0 to 2. 6 V. Correspondingly, the output current range is 50 to 426μA. The sensitivity of the PTAT current reference to Vdd is approximately 0. 021 7. The chip consumes a power of less than 1.3 mW for a 5 V supply, and occupies an area of 0. 112 mm^2.展开更多
An object segment similarity function is taken into account from the continuous media frames to measure the individual streaming profit of certain segment versions of a media object.Therefore,a new segment version-bas...An object segment similarity function is taken into account from the continuous media frames to measure the individual streaming profit of certain segment versions of a media object.Therefore,a new segment version-based transcoding(SVT)mechanism is derived for a quality of service(QoS)of client-centric media streaming in wireless mobile networks.The derived function utilizes the fuzzy similarity of certain segment versions of an object.This mechanism provides the effectiveness of reduction of the stream startup latency among segment versions,and the average access of each version.Thus,the proposed segment version transcoding mechanism reduces packet loss which in turn increases streaming performance and throughput.The performance of the partitioned segment versions is simulated and some segment versions are completed.The simulation results show that the proposed mechanism outperforms the other mechanisms in average cache hit ratio and in average startup latency ratio.展开更多
This paper presents a 10bit 100MS/s CMOS pipelined analog-to-digital converter （ADC） based on an improved 1.5bit/stage architecture. The ADC achieves a peak signal-to-noise-and-distortion ratio （SNDR） of 57dB and ...This paper presents a 10bit 100MS/s CMOS pipelined analog-to-digital converter （ADC） based on an improved 1.5bit/stage architecture. The ADC achieves a peak signal-to-noise-and-distortion ratio （SNDR） of 57dB and maintains 51dB up to 57MHz, the Nyquist frequency for a clock rate of 100Msample/s. The differential non-linearity （DNL） and integral non-linearity （INL） are typically measured as 0.3LSB and 1.0LSB, respectively. The ADC is implemented in a 0.18μm mixed-signal CMOS technology and occupies 0.76mm^2.展开更多
To improve the simulation accuracy of SIMULINK, a novel inclusive behavior model of an integrator is proposed that introduces the effects of different circuit nonidealities of a switched-capacitor sigma-delta modulato...To improve the simulation accuracy of SIMULINK, a novel inclusive behavior model of an integrator is proposed that introduces the effects of different circuit nonidealities of a switched-capacitor sigma-delta modulator into SIMULIK simulation. The nonlinear DC gain and nonlinear settling process are introduced into the op-amp module. The signaldependent charge injection and nonlinear resistance are introduced into the switch module. In addition, the noise source including flicker and thermal noise is introduced into system as an independent module. The novel model is verified by SIMULINK behavioral simulations. The results are compared with results from circuit level simulation in Cadence SPICE using TSMC 0.35μm mixed signal technology. It shows that the novel model succeeds in introducing the influences of the nonidealities into behavior simulation to more realistically describe the circuit performances and increase the accuracy of SIMULINK simulation.展开更多
文摘A 1.8V 8b 125Msample/s pipelined A/D converter is presented.Power efficiency is optimized by size scaling down scheme using low power single stage cascode amplifier with a gain boosted structure.Global clock tree and local generators are employed to avoid loss and overlap of clock period.The ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 49.5dB(7.9ENOB) for an input of 62MHz at full speed of 125MHz,consuming only 71mW.It is implemented in 0.18μm CMOS technology with a core area of 0.45mm 2.
文摘A complementary metal-oxide-semiconductor transistor （CMOS） voltage-to-current（VTC）converter with high linearity for current-mode analog and digital integrated circuits is described. A high gain operational amplifier （OPA） is utilized to form negative feedback. A proportional to absolute temperature （PTAT） current reference with transistors operated in a weak inversion is used as the bias circuit. The resistor and the OPA nonlinearity behavior are analyzed in detail. By optimizing parameters in OPA and adopting a small voltage coefficient polysilicon resistor as a linear device, a high linearity is achieved. The circuit is implemented in a standard 0. 6 μm CMOS technology. The low frequency gain of the OPA exceeds 90 dB. The test results indicate that the total harmonic distortion （THD）is 0. 000 2%. The common-mode input linearity range is 0 to 2. 6 V. Correspondingly, the output current range is 50 to 426μA. The sensitivity of the PTAT current reference to Vdd is approximately 0. 021 7. The chip consumes a power of less than 1.3 mW for a 5 V supply, and occupies an area of 0. 112 mm^2.
基金Project(2011)financially supported by Research Funds of Chonbuk National University,Korea
文摘An object segment similarity function is taken into account from the continuous media frames to measure the individual streaming profit of certain segment versions of a media object.Therefore,a new segment version-based transcoding(SVT)mechanism is derived for a quality of service(QoS)of client-centric media streaming in wireless mobile networks.The derived function utilizes the fuzzy similarity of certain segment versions of an object.This mechanism provides the effectiveness of reduction of the stream startup latency among segment versions,and the average access of each version.Thus,the proposed segment version transcoding mechanism reduces packet loss which in turn increases streaming performance and throughput.The performance of the partitioned segment versions is simulated and some segment versions are completed.The simulation results show that the proposed mechanism outperforms the other mechanisms in average cache hit ratio and in average startup latency ratio.
基金supported by the Research and Development Fund for the Applied Materials of Shanghai City(No.07SA16)~~
文摘This paper presents a 10bit 100MS/s CMOS pipelined analog-to-digital converter （ADC） based on an improved 1.5bit/stage architecture. The ADC achieves a peak signal-to-noise-and-distortion ratio （SNDR） of 57dB and maintains 51dB up to 57MHz, the Nyquist frequency for a clock rate of 100Msample/s. The differential non-linearity （DNL） and integral non-linearity （INL） are typically measured as 0.3LSB and 1.0LSB, respectively. The ADC is implemented in a 0.18μm mixed-signal CMOS technology and occupies 0.76mm^2.
基金the National Natural Science Foundation of China(No.90707002)~~
文摘To improve the simulation accuracy of SIMULINK, a novel inclusive behavior model of an integrator is proposed that introduces the effects of different circuit nonidealities of a switched-capacitor sigma-delta modulator into SIMULIK simulation. The nonlinear DC gain and nonlinear settling process are introduced into the op-amp module. The signaldependent charge injection and nonlinear resistance are introduced into the switch module. In addition, the noise source including flicker and thermal noise is introduced into system as an independent module. The novel model is verified by SIMULINK behavioral simulations. The results are compared with results from circuit level simulation in Cadence SPICE using TSMC 0.35μm mixed signal technology. It shows that the novel model succeeds in introducing the influences of the nonidealities into behavior simulation to more realistically describe the circuit performances and increase the accuracy of SIMULINK simulation.
