对日益复杂的消费产品不断增长的需求,引发了应用于消费类电子、汽车、工业和通讯领域的混合信号集成电路的需求急剧上升。时至今日,半导体制造商们把高速的数字逻辑电路和先进的模拟电路集成在一起制造出功能越来越强大的混合信号 IC...对日益复杂的消费产品不断增长的需求,引发了应用于消费类电子、汽车、工业和通讯领域的混合信号集成电路的需求急剧上升。时至今日,半导体制造商们把高速的数字逻辑电路和先进的模拟电路集成在一起制造出功能越来越强大的混合信号 IC。器件的复杂度在不断上升,但是其售价不可能随之飙升,半导体公司都发现他们面临着这样一个难题,即如何在降低测试成本的同时保证复杂的 IC 产品的质量。半导体公司发现他们需要改进测试构架、更先进的测试仪器、增强的测试开发环境以取得更高的测试产量并保证在测试上的投资有高的回报。为了应付这些挑战,顶尖的测试系统结合了高性能的架构和先进的测试仪器以取得高端测试仪的产量,而所花的成本只是传统 ATE 系统的一小部分。在 ATE 上开发应用程序时,新一代的混合信号测试仪不仅能降低测试成本而且可以灵活地适应将来不同应用场合下的需要,这将有力地保护你在测试设备、硬件资源、数字混合器件上的工程投资。本文将要讨论混合信号器件测试的主要趋势,及其对测试成本的影响,和一些新的测试结构,这些新的结构在满足当前测试需求的同时还将有能力灵活地适应未来正在形成的测试需求。展开更多
Phase locked loop(PLL) is a typical analog-digital mixed signal circuit and a method of conducting a top level system verification including PLL with standard digital simulator becomes especially significant.The behav...Phase locked loop(PLL) is a typical analog-digital mixed signal circuit and a method of conducting a top level system verification including PLL with standard digital simulator becomes especially significant.The behavioral level model(BLM) of the PLL in Verilog-HDL for pure digital simulator is innovated in this paper,and the design of PLL based clock and data recovery(CDR)circuit aided with jitter attenuation PLL for SerDes application is also presented.The CDR employs a dual-loop architecture where a frequency-locked loop acts as an acquisition aid to the phase-locked loop.To simultaneously meet jitter tolerance and jitter transfer specifications defined in G.8251 of optical transport network(ITU-T OTN),an additional jitter attenuation PLL is used.Simulation results show that the peak-to-peak jitter of the recovered clock and data is 5.17 ps and 2.3ps respectively.The core of the whole chip consumes 72 mA current from a 1.0V supply.展开更多
The present paper deals with the development of a modular, flexible and structured block to block approach for the study of regulators by implementing the different blocks on a DSP （digital signal processor）. The pr...The present paper deals with the development of a modular, flexible and structured block to block approach for the study of regulators by implementing the different blocks on a DSP （digital signal processor）. The proposed low-cost approach has been applied and validated by the implementation of an industrial regulator in a real time hardware-in-the-loop simulation of a mixed islanded power network including precise models of the hydraulic system. The studied network is constituted of three different types of electrical power generation systems and a consumer.展开更多
文摘对日益复杂的消费产品不断增长的需求,引发了应用于消费类电子、汽车、工业和通讯领域的混合信号集成电路的需求急剧上升。时至今日,半导体制造商们把高速的数字逻辑电路和先进的模拟电路集成在一起制造出功能越来越强大的混合信号 IC。器件的复杂度在不断上升,但是其售价不可能随之飙升,半导体公司都发现他们面临着这样一个难题,即如何在降低测试成本的同时保证复杂的 IC 产品的质量。半导体公司发现他们需要改进测试构架、更先进的测试仪器、增强的测试开发环境以取得更高的测试产量并保证在测试上的投资有高的回报。为了应付这些挑战,顶尖的测试系统结合了高性能的架构和先进的测试仪器以取得高端测试仪的产量,而所花的成本只是传统 ATE 系统的一小部分。在 ATE 上开发应用程序时,新一代的混合信号测试仪不仅能降低测试成本而且可以灵活地适应将来不同应用场合下的需要,这将有力地保护你在测试设备、硬件资源、数字混合器件上的工程投资。本文将要讨论混合信号器件测试的主要趋势,及其对测试成本的影响,和一些新的测试结构,这些新的结构在满足当前测试需求的同时还将有能力灵活地适应未来正在形成的测试需求。
基金Supported by the National High Technology Research and Development Programme of China(No.2011AA010301)the Research Foundation of Zhongxing Telecom Equipment Corporation and the National Natural Science Foundation of China(No.60976029)
文摘Phase locked loop(PLL) is a typical analog-digital mixed signal circuit and a method of conducting a top level system verification including PLL with standard digital simulator becomes especially significant.The behavioral level model(BLM) of the PLL in Verilog-HDL for pure digital simulator is innovated in this paper,and the design of PLL based clock and data recovery(CDR)circuit aided with jitter attenuation PLL for SerDes application is also presented.The CDR employs a dual-loop architecture where a frequency-locked loop acts as an acquisition aid to the phase-locked loop.To simultaneously meet jitter tolerance and jitter transfer specifications defined in G.8251 of optical transport network(ITU-T OTN),an additional jitter attenuation PLL is used.Simulation results show that the peak-to-peak jitter of the recovered clock and data is 5.17 ps and 2.3ps respectively.The core of the whole chip consumes 72 mA current from a 1.0V supply.
文摘The present paper deals with the development of a modular, flexible and structured block to block approach for the study of regulators by implementing the different blocks on a DSP （digital signal processor）. The proposed low-cost approach has been applied and validated by the implementation of an industrial regulator in a real time hardware-in-the-loop simulation of a mixed islanded power network including precise models of the hydraulic system. The studied network is constituted of three different types of electrical power generation systems and a consumer.
