This paper presents an efficient way to implement an interpolation filter in a 20bit ∑-△ DAC with an oversampling ratio of 128. A multistage structure is used to reduce the complexity of filter coefficients and the ...This paper presents an efficient way to implement an interpolation filter in a 20bit ∑-△ DAC with an oversampling ratio of 128. A multistage structure is used to reduce the complexity of filter coefficients and the fi- nite word length effect. A novel method based on mixed-radix number representation is proposed to realize a poly- phase multiplier-free half-band subfilter with a high resolution. This approach reduces the complexity of the con- trol system and saves chip area dramatically. The IC is realized in a standard 0.13μm CMOS process and the inter- polation filter occupies less than 0.63mm^2 . This realization has desirable properties of regularity with simple hard- ware devices which are suitable for VLSI and can be applied to many other high resolution data converters.展开更多
文摘This paper presents an efficient way to implement an interpolation filter in a 20bit ∑-△ DAC with an oversampling ratio of 128. A multistage structure is used to reduce the complexity of filter coefficients and the fi- nite word length effect. A novel method based on mixed-radix number representation is proposed to realize a poly- phase multiplier-free half-band subfilter with a high resolution. This approach reduces the complexity of the con- trol system and saves chip area dramatically. The IC is realized in a standard 0.13μm CMOS process and the inter- polation filter occupies less than 0.63mm^2 . This realization has desirable properties of regularity with simple hard- ware devices which are suitable for VLSI and can be applied to many other high resolution data converters.
