期刊文献+
共找到2篇文章
< 1 >
每页显示 20 50 100
0.5μmCMOS带隙基准电路设计 被引量:2
1
作者 张明英 朱刘松 邢立冬 《国外电子元器件》 2008年第12期79-81,共3页
依据带隙基准原理,采用华润上华(CSMC)0.5μm互补金属氧化物半导体(CMOS)工艺,设计了一种用于总线低电压差分信号(Bus Low Voltage Differential Signal,简称BLVDS)的总线收发器带隙基准电路。该电路有较低的温度系数和较高的电源抑制比... 依据带隙基准原理,采用华润上华(CSMC)0.5μm互补金属氧化物半导体(CMOS)工艺,设计了一种用于总线低电压差分信号(Bus Low Voltage Differential Signal,简称BLVDS)的总线收发器带隙基准电路。该电路有较低的温度系数和较高的电源抑制比。Hspice仿真结果表明,在电源电压VDD=3.3 V,温度T=25℃时,输出基准电压Vref=1.25 V。在温度范围为-45℃~+85℃时,输出电压的温度系数为20 pm/℃,电源电压的抑制比δ(PSRR)=-58.3 dB。 展开更多
关键词 模拟电路 电源 温度/带隙基准 抑制比 CMOS工艺
下载PDF
IC Implementation of a Programmable CMOS Voltage Reference 被引量:3
2
作者 张科 郭健民 +1 位作者 孔明 李文宏 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2007年第1期36-41,共6页
A new approach for the design and implementation of a programmable voltage reference based on an improved current mode bandgap voltage reference is presented. The circuit is simulated and fabricated with Chartered 0.... A new approach for the design and implementation of a programmable voltage reference based on an improved current mode bandgap voltage reference is presented. The circuit is simulated and fabricated with Chartered 0. 35μm mixed-signal technology. Measurements demonstrate that the temperature coefficient is ± 36. 3ppm/℃ from 0 to 100℃ when the VID inputs are 11110.As the supply voltage is varied from 2.7 to 5V, the voltage reference varies by about 5mV. The maximum glitch of the transient response is about 20mV at 125kHz. Depending on the state of the five VID inputs,an output voltage between 1.1 and 1.85V is programmed in increments of 25mV. 展开更多
关键词 voltage regulation modules current mode bandgap voltage reference temperature coefficient power supply rejection ratio programmable voltage reference
下载PDF
上一页 1 下一页 到第
使用帮助 返回顶部