This paper presents the design considerations and implementation of an area-efficient interpolator suitable for a delta-sigma D/A converter. In an effort to reduce the area and design complexity, a method for designin...This paper presents the design considerations and implementation of an area-efficient interpolator suitable for a delta-sigma D/A converter. In an effort to reduce the area and design complexity, a method for designing an FIR filter as a tapped cascaded interconnection of identical subfilters is modified. The proposed subfilter structure further minimizes the arithmetic number. Experimental results show that the proposed interpolator achieves the design specification,exhibiting high performance and hardware efficiency,and also has good noise rejection capability. The interpolation filter can be applied to a delta-sigma DAC and is fully functional.展开更多
A stereo 1.5bit delta-sigma digital-analog converter （△∑ DAC） integrated with a filterless class D power amplifier is introduced. It consumes no static power, and its maximum output power is 436mW with an 8Ω load...A stereo 1.5bit delta-sigma digital-analog converter （△∑ DAC） integrated with a filterless class D power amplifier is introduced. It consumes no static power, and its maximum output power is 436mW with an 8Ω load. Its output dynamic range exceeds 100dB. The circuit is implemented with a TSMC 0. 18μm process. The die area is 0. 28mme. The supply voltage is 1. gV for the digital part and 3.3V for class D.展开更多
This paper presents an efficient way to implement an interpolation filter in a 20bit ∑-△ DAC with an oversampling ratio of 128. A multistage structure is used to reduce the complexity of filter coefficients and the ...This paper presents an efficient way to implement an interpolation filter in a 20bit ∑-△ DAC with an oversampling ratio of 128. A multistage structure is used to reduce the complexity of filter coefficients and the fi- nite word length effect. A novel method based on mixed-radix number representation is proposed to realize a poly- phase multiplier-free half-band subfilter with a high resolution. This approach reduces the complexity of the con- trol system and saves chip area dramatically. The IC is realized in a standard 0.13μm CMOS process and the inter- polation filter occupies less than 0.63mm^2 . This realization has desirable properties of regularity with simple hard- ware devices which are suitable for VLSI and can be applied to many other high resolution data converters.展开更多
A novel current-source active power filter (APF) based on multi-modular converter with carrier phase-shifted SPWM (CPS-SPWM) technique is proposed. With this technique, the effect of equivalent high switching frequenc...A novel current-source active power filter (APF) based on multi-modular converter with carrier phase-shifted SPWM (CPS-SPWM) technique is proposed. With this technique, the effect of equivalent high switching frequency con-verter is obtained with low switching frequency converter. It is very promising in current-source APF that adopt super-conducting magnetic energy storage component.展开更多
If a somewhat fast moving object exists in a complicated tracking environment, snake's nodes may fall into the inaccurate local minima. We propose a mean shift snake algorithm to solve this problem. However, if th...If a somewhat fast moving object exists in a complicated tracking environment, snake's nodes may fall into the inaccurate local minima. We propose a mean shift snake algorithm to solve this problem. However, if the object goes beyond the limits of mean shift snake module operation in suc- cessive sequences, mean shift snake's nodes may also fall into the local minima in their moving to the new object position. This paper presents a motion compensation strategy by using particle filter; therefore a new Particle Filter Mean Shift Snake (PFMSS) algorithm is proposed which combines particle filter with mean shift snake to fulfill the estimation of the fast moving object contour. Firstly, the fast moving object is tracked by particle filter to create a coarse position which is used to initialize the mean shift algorithm. Secondly, the whole relevant motion information is used to compensate the snake's node positions. Finally, snake algorithm is used to extract the exact object contour and the useful information of the object is fed back. Some real world sequences are tested and the results show that the novel tracking method have a good performance with high accuracy in solving the fast moving problems in cluttered background.展开更多
An anti-aliasing filter for ADCs using a combination of active RC and analog FIR filters is presented in this letter. The first order active RC filter is set at 100kHz to minimize the die size and variations of linear...An anti-aliasing filter for ADCs using a combination of active RC and analog FIR filters is presented in this letter. The first order active RC filter is set at 100kHz to minimize the die size and variations of linear phase and gain in 0-4kHz passband. The 2-tap FIR filter provides more than -53dB attenuation at 2MHz +4kHz frequency range. The proposed filter achieved more than -76dB attenuation at sampling frequency with +0.01 phase linearity and +0.02dB gain variation within 0-4kHz bandwidth. The active die area of the fully differential filter is 0.17mm2 in 0.5um CMOS technology. The experimental and simulation results have been obtained and the feasibility of the proposed method is shown.展开更多
A novel single-phase Buck converter for power factor correction is proposed. It features simple control due to the constant duty ratio PWM used. It can obtain unity power factor by selecting a suitable LC filter at it...A novel single-phase Buck converter for power factor correction is proposed. It features simple control due to the constant duty ratio PWM used. It can obtain unity power factor by selecting a suitable LC filter at its input to force the voltage of capacitor to operate in discontinuous capacitor voltage mode. And by using another resonant LC filter at its output, it can not only eliminate the input current distortion at the vicinity of the zero crossing of the supply but also drastically reduce the 100 Hz output voltage ripple. The validity of analysis is confirmed by simulation results and experimental results.展开更多
This paper presents a new ZVT （zero-voltage transition） single-stage ac-to-dc converter using PWM （pulse width modulation） and HF （high frequency） transformer isolation with capacitive output filter. In this con...This paper presents a new ZVT （zero-voltage transition） single-stage ac-to-dc converter using PWM （pulse width modulation） and HF （high frequency） transformer isolation with capacitive output filter. In this converter a front-end power factor corrected boost stage integrates with a cascaded dc-to-dc bridge HF converter. The front-end boost converter operates in discontinuous current mode and ensures natural power factor correction with very simple control. The auxiliary circuit of this topology deals with very small power and is placed out of the main power path. As a result, the auxiliary circuit components have smaller power rating as opposed to main converter components. Also, output rectifier voltage is clamped to output voltage due to capacitive output filter. Identification and analyses of different operating modes of this converter are presented. Based on these analyses design example of a 50 kHz, 48 V, 1 kW ac-to-dc converter is presented. PSPICE simulation results of the designed converter are presented and explained to verify the performance of this converter.展开更多
This paper focuses on the implementation of a three-phase four-wire current-controlled Voltage Source Inverter （CC-VSI） as both power quality improvement and Photovoltaic （PV） energy extraction. For power quality ...This paper focuses on the implementation of a three-phase four-wire current-controlled Voltage Source Inverter （CC-VSI） as both power quality improvement and Photovoltaic （PV） energy extraction. For power quality improvement, the CC-VSI works as a grid current-controller shunt active power filter. Then, the PV array supported by the Hill- Climbing maximum power point tracking （MPPT） controller is coupled to the DC bus of the CC-VSI. The output of the MPPT controller is a DC voltage that determines the DC-bus voltage according to the PV maximum power. From computer simulation results, the CC-VSI is able to compensate for the harmonic and reactive power as well as to extract the PV maximum power.展开更多
In optical performance monitoring system,the analog to digital converter is needed to detect the peak of nanosecond pulse and get the signal envelope.A scheme based on a designed anti-aliasing filter and analog to dig...In optical performance monitoring system,the analog to digital converter is needed to detect the peak of nanosecond pulse and get the signal envelope.A scheme based on a designed anti-aliasing filter and analog to digital converter is proposed to broaden the nanosecond pulse and make it easier for the analog to digital converter to catch the peak of the nanosecond pulse.The experimental results demonstrate that,with the proposed scheme,the optical performance system needs less time to get the recovered eye-diagram of high speed optical data signal,and is robust to phase mismatch in the analog to digital converter circuit.展开更多
文摘This paper presents the design considerations and implementation of an area-efficient interpolator suitable for a delta-sigma D/A converter. In an effort to reduce the area and design complexity, a method for designing an FIR filter as a tapped cascaded interconnection of identical subfilters is modified. The proposed subfilter structure further minimizes the arithmetic number. Experimental results show that the proposed interpolator achieves the design specification,exhibiting high performance and hardware efficiency,and also has good noise rejection capability. The interpolation filter can be applied to a delta-sigma DAC and is fully functional.
文摘A stereo 1.5bit delta-sigma digital-analog converter （△∑ DAC） integrated with a filterless class D power amplifier is introduced. It consumes no static power, and its maximum output power is 436mW with an 8Ω load. Its output dynamic range exceeds 100dB. The circuit is implemented with a TSMC 0. 18μm process. The die area is 0. 28mme. The supply voltage is 1. gV for the digital part and 3.3V for class D.
文摘This paper presents an efficient way to implement an interpolation filter in a 20bit ∑-△ DAC with an oversampling ratio of 128. A multistage structure is used to reduce the complexity of filter coefficients and the fi- nite word length effect. A novel method based on mixed-radix number representation is proposed to realize a poly- phase multiplier-free half-band subfilter with a high resolution. This approach reduces the complexity of the con- trol system and saves chip area dramatically. The IC is realized in a standard 0.13μm CMOS process and the inter- polation filter occupies less than 0.63mm^2 . This realization has desirable properties of regularity with simple hard- ware devices which are suitable for VLSI and can be applied to many other high resolution data converters.
文摘A novel current-source active power filter (APF) based on multi-modular converter with carrier phase-shifted SPWM (CPS-SPWM) technique is proposed. With this technique, the effect of equivalent high switching frequency con-verter is obtained with low switching frequency converter. It is very promising in current-source APF that adopt super-conducting magnetic energy storage component.
基金Supported by the National Natural Science Foundation of China (No. 60672094)
文摘If a somewhat fast moving object exists in a complicated tracking environment, snake's nodes may fall into the inaccurate local minima. We propose a mean shift snake algorithm to solve this problem. However, if the object goes beyond the limits of mean shift snake module operation in suc- cessive sequences, mean shift snake's nodes may also fall into the local minima in their moving to the new object position. This paper presents a motion compensation strategy by using particle filter; therefore a new Particle Filter Mean Shift Snake (PFMSS) algorithm is proposed which combines particle filter with mean shift snake to fulfill the estimation of the fast moving object contour. Firstly, the fast moving object is tracked by particle filter to create a coarse position which is used to initialize the mean shift algorithm. Secondly, the whole relevant motion information is used to compensate the snake's node positions. Finally, snake algorithm is used to extract the exact object contour and the useful information of the object is fed back. Some real world sequences are tested and the results show that the novel tracking method have a good performance with high accuracy in solving the fast moving problems in cluttered background.
基金Foundation for University Key Teacher by the Ministry of Education of China
文摘An anti-aliasing filter for ADCs using a combination of active RC and analog FIR filters is presented in this letter. The first order active RC filter is set at 100kHz to minimize the die size and variations of linear phase and gain in 0-4kHz passband. The 2-tap FIR filter provides more than -53dB attenuation at 2MHz +4kHz frequency range. The proposed filter achieved more than -76dB attenuation at sampling frequency with +0.01 phase linearity and +0.02dB gain variation within 0-4kHz bandwidth. The active die area of the fully differential filter is 0.17mm2 in 0.5um CMOS technology. The experimental and simulation results have been obtained and the feasibility of the proposed method is shown.
文摘A novel single-phase Buck converter for power factor correction is proposed. It features simple control due to the constant duty ratio PWM used. It can obtain unity power factor by selecting a suitable LC filter at its input to force the voltage of capacitor to operate in discontinuous capacitor voltage mode. And by using another resonant LC filter at its output, it can not only eliminate the input current distortion at the vicinity of the zero crossing of the supply but also drastically reduce the 100 Hz output voltage ripple. The validity of analysis is confirmed by simulation results and experimental results.
文摘This paper presents a new ZVT （zero-voltage transition） single-stage ac-to-dc converter using PWM （pulse width modulation） and HF （high frequency） transformer isolation with capacitive output filter. In this converter a front-end power factor corrected boost stage integrates with a cascaded dc-to-dc bridge HF converter. The front-end boost converter operates in discontinuous current mode and ensures natural power factor correction with very simple control. The auxiliary circuit of this topology deals with very small power and is placed out of the main power path. As a result, the auxiliary circuit components have smaller power rating as opposed to main converter components. Also, output rectifier voltage is clamped to output voltage due to capacitive output filter. Identification and analyses of different operating modes of this converter are presented. Based on these analyses design example of a 50 kHz, 48 V, 1 kW ac-to-dc converter is presented. PSPICE simulation results of the designed converter are presented and explained to verify the performance of this converter.
文摘This paper focuses on the implementation of a three-phase four-wire current-controlled Voltage Source Inverter （CC-VSI） as both power quality improvement and Photovoltaic （PV） energy extraction. For power quality improvement, the CC-VSI works as a grid current-controller shunt active power filter. Then, the PV array supported by the Hill- Climbing maximum power point tracking （MPPT） controller is coupled to the DC bus of the CC-VSI. The output of the MPPT controller is a DC voltage that determines the DC-bus voltage according to the PV maximum power. From computer simulation results, the CC-VSI is able to compensate for the harmonic and reactive power as well as to extract the PV maximum power.
基金supported by National 863 Program of China(2013AA013401),P.R.ChinaNational Natural Science Foundation of China under Grant No.61177067,No.61027007,and No.61331010
文摘In optical performance monitoring system,the analog to digital converter is needed to detect the peak of nanosecond pulse and get the signal envelope.A scheme based on a designed anti-aliasing filter and analog to digital converter is proposed to broaden the nanosecond pulse and make it easier for the analog to digital converter to catch the peak of the nanosecond pulse.The experimental results demonstrate that,with the proposed scheme,the optical performance system needs less time to get the recovered eye-diagram of high speed optical data signal,and is robust to phase mismatch in the analog to digital converter circuit.
