The on-resistance degradations of the p-type lateral extended drain MOS transistor （pLEDMOS） with thick gate oxide under different hot carrier stress conditions are different, which has been experimentally investiga...The on-resistance degradations of the p-type lateral extended drain MOS transistor （pLEDMOS） with thick gate oxide under different hot carrier stress conditions are different, which has been experimentally investigated. This difference results from the interface trap generation and the hot electron injection, and trapping into the thick gate oxide and field oxide of the pLEDMOS transistor. An improved method to reduce the on-resistance degradations is also presented, which uses the field oxide as the gate oxide instead of the thick gate oxide. The effects are analyzed with a MEDICI simulator.展开更多
It is shown that traps are generated asymmetrically in the thin gate oxides with different thickness during high field degradation,as well as the multi-mechanism plays role in the Stress Induced Leakage Current ...It is shown that traps are generated asymmetrically in the thin gate oxides with different thickness during high field degradation,as well as the multi-mechanism plays role in the Stress Induced Leakage Current (SILC).These factors perform differently in gate oxide of different thickness.A comparison is drew between several analyzing models.Trap assisted tunneling is preferred for thinner samples,while Pool-Frankel like mechanism or thermal emission mechanism should apply to the thick ones.展开更多
A high performance 70nm CMOS device has been demonstrated for the first time in the continent, China. Some innovations in techniques are applied to restrain the short channel effect and improve the driving ability, ...A high performance 70nm CMOS device has been demonstrated for the first time in the continent, China. Some innovations in techniques are applied to restrain the short channel effect and improve the driving ability, such as 3nm nitrided oxide, dual poly Si gate electrode, novel super steep retrograde channel doping by heavy ion implantation, ultra shallow S/D extension formed by Ge PAI(Pre Amorphism Implantation) plus LEI(Low Energy Implantation), thin and low resistance Ti SALICIDE by Ge PAI and special cleaning, etc. The shortest channel length of the CMOS device is 70nm. The threshold voltages, G m and off current are 0 28V,490mS·mm -1 and 0 08nA/μm for NMOS and -0 3V,340mS·mm -1 and 0 2nA/μm for PMOS, respectively. Delays of 23 5ps/stage at 1 5V, 17 5ps/stage at 2 0V and 12 5ps/stage at 3V are achieved in the 57 stage unloaded 100nm CMOS ring oscillator circuits.展开更多
By measurement,we investigate the characteristics and location of gate oxide damage induced by snapback stress. The damage incurred during stress causes device degradation that follows an approximate power law with st...By measurement,we investigate the characteristics and location of gate oxide damage induced by snapback stress. The damage incurred during stress causes device degradation that follows an approximate power law with stress time. Oxide traps generated by stress will cause the increase of stress-induced leakage current and the decrease of Qbd （charge to breakdown）,and it may also cause the degradation of off-state drain leakage current. Stress-induced gate oxide damage is located not only in the drain side but also in the source side. The tertiary electrons generated by hot holes move toward Si-SiO2 interface under the electrical field toward the substrate,which explains the source side gate oxide damage.展开更多
In order to determine the role of alginate-derived oligosaccharides (ADO) in drought stress resistance of tomato (Ly-copersicon esculentum Miller) seedlings, the leaves were exposed to different concentrations of ADO ...In order to determine the role of alginate-derived oligosaccharides (ADO) in drought stress resistance of tomato (Ly-copersicon esculentum Miller) seedlings, the leaves were exposed to different concentrations of ADO (0.05%, 0.10%, 0.20%, 0.30% and 0.50%) after drought stress was simulated by exposing the roots to 0.6 molL-1 PEG-6000 solution for 6 h. Changes in biomass, electrolyte leakage and malondialdehyde (MDA), free proline, total soluble sugars (TSS) and abscisic acid (ABA), the enzyme activities of catalase (CAT), superoxide dismutase (SOD), peroxidase (POD) and phenylalanine ammonia-lyase (PAL) were measured to investigate the effects of ADO treatment. The results showed that the treatment with an ADO concentration of 0.20% exhibited the highest performance of drought stress resistance in the tomato seedlings by decreasing the electrolyte leakage and the concentration of MDA, increasing the contents of free proline, TSS and ABA, and increasing the activities of CAT, SOD, POD and PAL after treatment with ADO. It is suggested that changes in electrolyte leakage, MDA, osmotic solutes, ABA, anti-oxidative enzyme and PAL activities were responsible for the increased drought stress resistance in tomato seedlings. To our best knowledge, this is the first report of the effect of ADO treatment on enhancing the drought stress resistance of tomato seedlings.展开更多
The paper describes a method for monitoring CO2 leakage in geological carbon dioxide sequestration. A real time monitoring parameter, apparent leakage flux(ALF), is presented to monitor abnormal CO2 leakage, which can...The paper describes a method for monitoring CO2 leakage in geological carbon dioxide sequestration. A real time monitoring parameter, apparent leakage flux(ALF), is presented to monitor abnormal CO2 leakage, which can be calculated by atmospheric CO2 and O2 data. The computation shows that all ALF values are close to zero-line without the leakage. With a step change or linear perturbation of concentration to the initial CO2 concentration data with no leakage, ALF will deviate from background line. Perturbation tests prove that ALF method is sensitive to linear perturbation but insensitive to step change of concentration. An improved method is proposed based on real time analysis of surplus CO2 concentration in least square regression process, called apparent leakage flux from surplus analysis(ALFs), which is sensitive to both step perturbation and linear perturbations of concentration. ALF is capable of detecting concentration increase when the leakage occurs while ALFs is useful in all periods of leakage. Both ALF and ALFs are potential approaches to monitor CO2 leakage in geosequestration project.展开更多
As dimensions of the metal-oxide-semiconductor field-effect transistor (MOSFET) are scaling down and the thickness of gate oxide is decreased,the gate leakage becomes more and more prominent and has been one of the mo...As dimensions of the metal-oxide-semiconductor field-effect transistor (MOSFET) are scaling down and the thickness of gate oxide is decreased,the gate leakage becomes more and more prominent and has been one of the most important limiting factors to MOSFET and circuits lifetime.Based on reliability theory and experiments,the direct tunneling current in lightly-doped drain (LDD) NMOSFET with 1.4 nm gate oxide fabricated by 90 nm complementary metal oxide semiconductor (CMOS) process was studied in depth.High-precision semiconductor parameter analyzer was used to conduct the tests.Law of variation of the direct tunneling (DT) current with channel length,channel width,measuring voltage,drain bias and reverse substrate bias was revealed.The results show that the change of the DT current obeys index law;there is a linear relationship between gate current and channel dimension;drain bias and substrate bias can reduce the gate current.展开更多
This paper proposes a low-power MOS current mode logic （MCML） circuit with sleep-transistor to reduce the leakage current. The sleep-transistor is used to high-threshold voltage transistor to minimize the leakage cu...This paper proposes a low-power MOS current mode logic （MCML） circuit with sleep-transistor to reduce the leakage current. The sleep-transistor is used to high-threshold voltage transistor to minimize the leakage current. The 16× 16 bit parallel multiplier is designed with the proposed technology. Comparing with the previous MCML circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/258. This circuit is designed with Samsung 0.35 um complementary metal oxide semiconductor （CMOS） process. The validity and effectiveness are verified through the HSPICE simulation.展开更多
A buried-oxide trench-gate bipolar-mode JFET （BTB-JFET） with an oxide layer buried under the gate region to reduce the gate-drain capacitance Cgd is proposed. Simulations with a resistive load circuit for power loss...A buried-oxide trench-gate bipolar-mode JFET （BTB-JFET） with an oxide layer buried under the gate region to reduce the gate-drain capacitance Cgd is proposed. Simulations with a resistive load circuit for power loss comparison at high frequency application are performed with 20V-rated power switching devices,including a BTB-JFET,a trench MOSFET （T-MOSFET） generally applied in present industry, and a conventional trench-gate bipolar-mode JFET （TB-JFET） without buried oxide,for the first time. The simulation results indicate that the switching power loss of the normally-on BTB-JFET is improved by 37% and 14% at 1MHz compared to the T-MOSFET and the normally-on TB-JFET, respectively. In order to demonstrate the validity of the simulation, the normally-on TB-JFET and BTB-JFET have been fabricated successfully for the first time, where the buried oxide structure is realized by thermal oxidation. The experimental results show that the Cgd of the BTB-JFET is decreased by 45% from that of the TB-JFET at zero source-drain bias. Compared to the TB-JFET,the switching time and switching power loss of the BTB-JFET decrease approximately by 7. 4% and 11% at 1MHz,respectively. Therefore,the normally-on BTB-JFET could be pointing to a new direction for the R＆D of low volt- age and high frequency switching devices.展开更多
文摘The on-resistance degradations of the p-type lateral extended drain MOS transistor （pLEDMOS） with thick gate oxide under different hot carrier stress conditions are different, which has been experimentally investigated. This difference results from the interface trap generation and the hot electron injection, and trapping into the thick gate oxide and field oxide of the pLEDMOS transistor. An improved method to reduce the on-resistance degradations is also presented, which uses the field oxide as the gate oxide instead of the thick gate oxide. The effects are analyzed with a MEDICI simulator.
文摘It is shown that traps are generated asymmetrically in the thin gate oxides with different thickness during high field degradation,as well as the multi-mechanism plays role in the Stress Induced Leakage Current (SILC).These factors perform differently in gate oxide of different thickness.A comparison is drew between several analyzing models.Trap assisted tunneling is preferred for thinner samples,while Pool-Frankel like mechanism or thermal emission mechanism should apply to the thick ones.
文摘A high performance 70nm CMOS device has been demonstrated for the first time in the continent, China. Some innovations in techniques are applied to restrain the short channel effect and improve the driving ability, such as 3nm nitrided oxide, dual poly Si gate electrode, novel super steep retrograde channel doping by heavy ion implantation, ultra shallow S/D extension formed by Ge PAI(Pre Amorphism Implantation) plus LEI(Low Energy Implantation), thin and low resistance Ti SALICIDE by Ge PAI and special cleaning, etc. The shortest channel length of the CMOS device is 70nm. The threshold voltages, G m and off current are 0 28V,490mS·mm -1 and 0 08nA/μm for NMOS and -0 3V,340mS·mm -1 and 0 2nA/μm for PMOS, respectively. Delays of 23 5ps/stage at 1 5V, 17 5ps/stage at 2 0V and 12 5ps/stage at 3V are achieved in the 57 stage unloaded 100nm CMOS ring oscillator circuits.
文摘By measurement,we investigate the characteristics and location of gate oxide damage induced by snapback stress. The damage incurred during stress causes device degradation that follows an approximate power law with stress time. Oxide traps generated by stress will cause the increase of stress-induced leakage current and the decrease of Qbd （charge to breakdown）,and it may also cause the degradation of off-state drain leakage current. Stress-induced gate oxide damage is located not only in the drain side but also in the source side. The tertiary electrons generated by hot holes move toward Si-SiO2 interface under the electrical field toward the substrate,which explains the source side gate oxide damage.
基金supported by the National Natural Science Foundation of China (No. 30771646)Shandong Province Independent Innovation Project with the title of ‘Industrialization development of several special seaweeds biological products using integrated technologies’
文摘In order to determine the role of alginate-derived oligosaccharides (ADO) in drought stress resistance of tomato (Ly-copersicon esculentum Miller) seedlings, the leaves were exposed to different concentrations of ADO (0.05%, 0.10%, 0.20%, 0.30% and 0.50%) after drought stress was simulated by exposing the roots to 0.6 molL-1 PEG-6000 solution for 6 h. Changes in biomass, electrolyte leakage and malondialdehyde (MDA), free proline, total soluble sugars (TSS) and abscisic acid (ABA), the enzyme activities of catalase (CAT), superoxide dismutase (SOD), peroxidase (POD) and phenylalanine ammonia-lyase (PAL) were measured to investigate the effects of ADO treatment. The results showed that the treatment with an ADO concentration of 0.20% exhibited the highest performance of drought stress resistance in the tomato seedlings by decreasing the electrolyte leakage and the concentration of MDA, increasing the contents of free proline, TSS and ABA, and increasing the activities of CAT, SOD, POD and PAL after treatment with ADO. It is suggested that changes in electrolyte leakage, MDA, osmotic solutes, ABA, anti-oxidative enzyme and PAL activities were responsible for the increased drought stress resistance in tomato seedlings. To our best knowledge, this is the first report of the effect of ADO treatment on enhancing the drought stress resistance of tomato seedlings.
基金Supported by the National Natural Science Foundation of China(51276141,20936004)
文摘The paper describes a method for monitoring CO2 leakage in geological carbon dioxide sequestration. A real time monitoring parameter, apparent leakage flux(ALF), is presented to monitor abnormal CO2 leakage, which can be calculated by atmospheric CO2 and O2 data. The computation shows that all ALF values are close to zero-line without the leakage. With a step change or linear perturbation of concentration to the initial CO2 concentration data with no leakage, ALF will deviate from background line. Perturbation tests prove that ALF method is sensitive to linear perturbation but insensitive to step change of concentration. An improved method is proposed based on real time analysis of surplus CO2 concentration in least square regression process, called apparent leakage flux from surplus analysis(ALFs), which is sensitive to both step perturbation and linear perturbations of concentration. ALF is capable of detecting concentration increase when the leakage occurs while ALFs is useful in all periods of leakage. Both ALF and ALFs are potential approaches to monitor CO2 leakage in geosequestration project.
基金Project(61074051)supported by the National Natural Science Foundation of ChinaProject(10C0709)supported by the Scientific Research Fund of Education Department of Hunan Province,ChinaProject(2011GK3058)supported by the Science and Technology Plan of Hunan Province,China
文摘As dimensions of the metal-oxide-semiconductor field-effect transistor (MOSFET) are scaling down and the thickness of gate oxide is decreased,the gate leakage becomes more and more prominent and has been one of the most important limiting factors to MOSFET and circuits lifetime.Based on reliability theory and experiments,the direct tunneling current in lightly-doped drain (LDD) NMOSFET with 1.4 nm gate oxide fabricated by 90 nm complementary metal oxide semiconductor (CMOS) process was studied in depth.High-precision semiconductor parameter analyzer was used to conduct the tests.Law of variation of the direct tunneling (DT) current with channel length,channel width,measuring voltage,drain bias and reverse substrate bias was revealed.The results show that the change of the DT current obeys index law;there is a linear relationship between gate current and channel dimension;drain bias and substrate bias can reduce the gate current.
文摘This paper proposes a low-power MOS current mode logic （MCML） circuit with sleep-transistor to reduce the leakage current. The sleep-transistor is used to high-threshold voltage transistor to minimize the leakage current. The 16× 16 bit parallel multiplier is designed with the proposed technology. Comparing with the previous MCML circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/258. This circuit is designed with Samsung 0.35 um complementary metal oxide semiconductor （CMOS） process. The validity and effectiveness are verified through the HSPICE simulation.
文摘A buried-oxide trench-gate bipolar-mode JFET （BTB-JFET） with an oxide layer buried under the gate region to reduce the gate-drain capacitance Cgd is proposed. Simulations with a resistive load circuit for power loss comparison at high frequency application are performed with 20V-rated power switching devices,including a BTB-JFET,a trench MOSFET （T-MOSFET） generally applied in present industry, and a conventional trench-gate bipolar-mode JFET （TB-JFET） without buried oxide,for the first time. The simulation results indicate that the switching power loss of the normally-on BTB-JFET is improved by 37% and 14% at 1MHz compared to the T-MOSFET and the normally-on TB-JFET, respectively. In order to demonstrate the validity of the simulation, the normally-on TB-JFET and BTB-JFET have been fabricated successfully for the first time, where the buried oxide structure is realized by thermal oxidation. The experimental results show that the Cgd of the BTB-JFET is decreased by 45% from that of the TB-JFET at zero source-drain bias. Compared to the TB-JFET,the switching time and switching power loss of the BTB-JFET decrease approximately by 7. 4% and 11% at 1MHz,respectively. Therefore,the normally-on BTB-JFET could be pointing to a new direction for the R＆D of low volt- age and high frequency switching devices.
