ISO 11607-2:2006要求对无菌医疗器械的无菌屏障系统的密封过程进行确认。确定包装材料的最佳热封参数则是进行这一确认的重要内容之一。本文通过实验室开展的实际试验,介绍了用ASTMF 2029给出的试验方法建立形成一系列热封条件下得出...ISO 11607-2:2006要求对无菌医疗器械的无菌屏障系统的密封过程进行确认。确定包装材料的最佳热封参数则是进行这一确认的重要内容之一。本文通过实验室开展的实际试验,介绍了用ASTMF 2029给出的试验方法建立形成一系列热封条件下得出的热封强度对温度的热封曲线,并附以实物样品,以此确定医疗器械软包装材料的最佳热封参数。展开更多
High performance can be obtained for the integrated power electronics module（IPEM） by using a three-dimensional packaging structure instead of a planar structure. A three- dimensional packaged half bridge-IPEM （HB-...High performance can be obtained for the integrated power electronics module（IPEM） by using a three-dimensional packaging structure instead of a planar structure. A three- dimensional packaged half bridge-IPEM （HB-IPEM）, consisting of two chip scale packaged MOSFETs and the corresponding gate driver and protection circuits, is fabricated at the laboratory. The reliability of the IPEM is controlled from the shape design of solder joints and the control of assembly process parameters. The parasitic parameters are extracted using Agilent 4395A impedance analyzer for building the parasitic parameter model of the HB- IPEM. A 12 V/3 A output synchronous rectifier Buck converter using the HB-IPEM is built to test the electrical performance of the HB-IPEM. Low voltage spikes on two MOSFETs illustrate that the three-dimensional package of the HB-IPEM can decrease parasitic inductance. Temperature distribution simulation results of the HB-IPEM using FLOTHERM are given. Heat dissipation of the solder joints makes the peak junction temperature of the chip drop obviously. The package realizes three-dimensional heat dissipation and has better thermal management.展开更多
基金Fok Ying Tung Education Foundation(No.91058)the Natural Science Foundation of High Education Institutions of Jiangsu Province(No.08KJD470004)Qing Lan Project of Jiangsu Province of 2008
文摘High performance can be obtained for the integrated power electronics module（IPEM） by using a three-dimensional packaging structure instead of a planar structure. A three- dimensional packaged half bridge-IPEM （HB-IPEM）, consisting of two chip scale packaged MOSFETs and the corresponding gate driver and protection circuits, is fabricated at the laboratory. The reliability of the IPEM is controlled from the shape design of solder joints and the control of assembly process parameters. The parasitic parameters are extracted using Agilent 4395A impedance analyzer for building the parasitic parameter model of the HB- IPEM. A 12 V/3 A output synchronous rectifier Buck converter using the HB-IPEM is built to test the electrical performance of the HB-IPEM. Low voltage spikes on two MOSFETs illustrate that the three-dimensional package of the HB-IPEM can decrease parasitic inductance. Temperature distribution simulation results of the HB-IPEM using FLOTHERM are given. Heat dissipation of the solder joints makes the peak junction temperature of the chip drop obviously. The package realizes three-dimensional heat dissipation and has better thermal management.
