阐述IEC 60364-4-41:2005《Lowvoltage electrical installations—Part 4-41:Protection for safety—Protection against electric shock》标准规定TT系统内由同一保护电器所保护的所有电气设备必须采用共用接地防电击的原由,举例说...阐述IEC 60364-4-41:2005《Lowvoltage electrical installations—Part 4-41:Protection for safety—Protection against electric shock》标准规定TT系统内由同一保护电器所保护的所有电气设备必须采用共用接地防电击的原由,举例说明户外农电装置、施工场地、路灯等TT系统应用中的接地和防电击实施方案。着重叙述路灯TT系统共用接地并采用过电流防护电器兼防电击在我国的特殊现实意义。展开更多
Breakdown voltage （Vbd） and charge to breakdown （Qbd） are two parameters often used to evaluate gate oxide reliability. In this paper,we investigate the effects of measurement methods on Vbd and Qbd of the gate ox...Breakdown voltage （Vbd） and charge to breakdown （Qbd） are two parameters often used to evaluate gate oxide reliability. In this paper,we investigate the effects of measurement methods on Vbd and Qbd of the gate oxide of a 0.18μm dual gate CMOS process. Voltage ramps （V-ramp） and current ramps （J-ramp） are used to evaluate gate oxide reliability. The thin and thick gate oxides are all evaluated in the accumulation condition. Our experimental results show that the measurement methods affect Vbd only slightly but affect Qbd seriously,as do the measurement conditions.This affects the I-t curves obtained with the J-ramp and V-ramp methods. From the I-t curve,it can be seen that Qbd obtained using a J-ramp is much bigger than that with a V-ramp. At the same time, the Weibull slopes of Qbd are definitely smaller than those of Vbd. This means that Vbd is more reliable than Qbd, Thus we should be careful to use Qbd to evaluate the reliability of 0.18μm or beyond CMOS process gate oxide.展开更多
By measurement,we investigate the characteristics and location of gate oxide damage induced by snapback stress. The damage incurred during stress causes device degradation that follows an approximate power law with st...By measurement,we investigate the characteristics and location of gate oxide damage induced by snapback stress. The damage incurred during stress causes device degradation that follows an approximate power law with stress time. Oxide traps generated by stress will cause the increase of stress-induced leakage current and the decrease of Qbd （charge to breakdown）,and it may also cause the degradation of off-state drain leakage current. Stress-induced gate oxide damage is located not only in the drain side but also in the source side. The tertiary electrons generated by hot holes move toward Si-SiO2 interface under the electrical field toward the substrate,which explains the source side gate oxide damage.展开更多
The purpose of this work relates to study on the characteristics of ultra thin gate oxide (2 5nm thickness) and the effect of metal Al,Zr,and Ta contamination on GOI.The controlled metallic contamination experiments...The purpose of this work relates to study on the characteristics of ultra thin gate oxide (2 5nm thickness) and the effect of metal Al,Zr,and Ta contamination on GOI.The controlled metallic contamination experiments are carried out by depositing a few ppm contaminated metal and low pH solutions on the wafers.The maximum metal surface concentration is controlled at about 10 12 cm -2 level in order to simulate metal contamination during ultra clean processing.A ramped current stress for intrinsic charge to breakdown measurements with gate injection mode is used to examine the characteristics of these ultra thin gate oxides and the effect of metal contamination on GOI.It is the first time to investigate the influence of metal Zr and Ta contamination on 2 5nm ultra thin gate oxide.It is demonstrated that there is little effect of Al contamination on GOI,while Zr contamination is the most detrimental to GOI,and early breakdown has happened to wafers contaminated by Ta.展开更多
p-GaN cap layer has been recognized as a commercial technology to manufacture enhanced-mode(E-mode)AlGaN/GaN high electron mobility transistor(HEMT);however,the difficult activation of Mg doping and etching damage of ...p-GaN cap layer has been recognized as a commercial technology to manufacture enhanced-mode(E-mode)AlGaN/GaN high electron mobility transistor(HEMT);however,the difficult activation of Mg doping and etching damage of p-GaN limit the further improvement of device performance.Thus,the more cost-effective cap layer has attracted wide attention in GaN-based HEMT.In this paper,p-type tin monoxide(p-SnO)was firstly investigated as a gate cap to realize E-mode AlGaN/GaN HEMT by both Silvaco simulation and experiment.Simulation results show that by simply adjusting the thickness(50 to 200 nm)or the doping concentration(3×10^(17)to 3×10^(18)cm^(-3))of p-SnO,the threshold voltage(V_(th))of HEMT can be continuously adjusted in the range from zero to 10 V.Simultaneously,the device demonstrated a drain current density above 120 mA mm^(-1),a gate breakdown voltage(V_(BG))of 7.5 V and a device breakdown voltage(V_(B))of 2470 V.What is more,the etching-free AlGaN/GaN HEMT with sputtered p-SnO gate cap were fabricated,and achieved a positive V_(th) of 1 V,V_(BG) of 4.2 V and V_(B) of 420 V,which confirms the application potential of the p-SnO film as a gate cap layer for E-mode GaN-based HEMT.This work is instructive to the design and manufacture of p-oxide gate cap E-mode AlGaN/GaN HEMT with low cost.展开更多
文摘阐述IEC 60364-4-41:2005《Lowvoltage electrical installations—Part 4-41:Protection for safety—Protection against electric shock》标准规定TT系统内由同一保护电器所保护的所有电气设备必须采用共用接地防电击的原由,举例说明户外农电装置、施工场地、路灯等TT系统应用中的接地和防电击实施方案。着重叙述路灯TT系统共用接地并采用过电流防护电器兼防电击在我国的特殊现实意义。
文摘Breakdown voltage （Vbd） and charge to breakdown （Qbd） are two parameters often used to evaluate gate oxide reliability. In this paper,we investigate the effects of measurement methods on Vbd and Qbd of the gate oxide of a 0.18μm dual gate CMOS process. Voltage ramps （V-ramp） and current ramps （J-ramp） are used to evaluate gate oxide reliability. The thin and thick gate oxides are all evaluated in the accumulation condition. Our experimental results show that the measurement methods affect Vbd only slightly but affect Qbd seriously,as do the measurement conditions.This affects the I-t curves obtained with the J-ramp and V-ramp methods. From the I-t curve,it can be seen that Qbd obtained using a J-ramp is much bigger than that with a V-ramp. At the same time, the Weibull slopes of Qbd are definitely smaller than those of Vbd. This means that Vbd is more reliable than Qbd, Thus we should be careful to use Qbd to evaluate the reliability of 0.18μm or beyond CMOS process gate oxide.
文摘By measurement,we investigate the characteristics and location of gate oxide damage induced by snapback stress. The damage incurred during stress causes device degradation that follows an approximate power law with stress time. Oxide traps generated by stress will cause the increase of stress-induced leakage current and the decrease of Qbd （charge to breakdown）,and it may also cause the degradation of off-state drain leakage current. Stress-induced gate oxide damage is located not only in the drain side but also in the source side. The tertiary electrons generated by hot holes move toward Si-SiO2 interface under the electrical field toward the substrate,which explains the source side gate oxide damage.
文摘The purpose of this work relates to study on the characteristics of ultra thin gate oxide (2 5nm thickness) and the effect of metal Al,Zr,and Ta contamination on GOI.The controlled metallic contamination experiments are carried out by depositing a few ppm contaminated metal and low pH solutions on the wafers.The maximum metal surface concentration is controlled at about 10 12 cm -2 level in order to simulate metal contamination during ultra clean processing.A ramped current stress for intrinsic charge to breakdown measurements with gate injection mode is used to examine the characteristics of these ultra thin gate oxides and the effect of metal contamination on GOI.It is the first time to investigate the influence of metal Zr and Ta contamination on 2 5nm ultra thin gate oxide.It is demonstrated that there is little effect of Al contamination on GOI,while Zr contamination is the most detrimental to GOI,and early breakdown has happened to wafers contaminated by Ta.
基金supported by the National Natural Science Foundation of China(62003151,61925404,62074122,and 61904139)the Key Research and Development Program in Shaanxi Province(2016KTZDGY-03-01)。
文摘p-GaN cap layer has been recognized as a commercial technology to manufacture enhanced-mode(E-mode)AlGaN/GaN high electron mobility transistor(HEMT);however,the difficult activation of Mg doping and etching damage of p-GaN limit the further improvement of device performance.Thus,the more cost-effective cap layer has attracted wide attention in GaN-based HEMT.In this paper,p-type tin monoxide(p-SnO)was firstly investigated as a gate cap to realize E-mode AlGaN/GaN HEMT by both Silvaco simulation and experiment.Simulation results show that by simply adjusting the thickness(50 to 200 nm)or the doping concentration(3×10^(17)to 3×10^(18)cm^(-3))of p-SnO,the threshold voltage(V_(th))of HEMT can be continuously adjusted in the range from zero to 10 V.Simultaneously,the device demonstrated a drain current density above 120 mA mm^(-1),a gate breakdown voltage(V_(BG))of 7.5 V and a device breakdown voltage(V_(B))of 2470 V.What is more,the etching-free AlGaN/GaN HEMT with sputtered p-SnO gate cap were fabricated,and achieved a positive V_(th) of 1 V,V_(BG) of 4.2 V and V_(B) of 420 V,which confirms the application potential of the p-SnO film as a gate cap layer for E-mode GaN-based HEMT.This work is instructive to the design and manufacture of p-oxide gate cap E-mode AlGaN/GaN HEMT with low cost.
