一款纯电动城市客车整车电功耗测试

设计了一款纯电动城市客车整车电功耗测试技术方案,并测试分析了在中国典型城市公交工况下的整车电功耗。通过整车电功耗测试来评估整车能耗量,预估纯电动客车整车续驶里程,为合理安排纯电动客车运营规划提供数据。

交直交变换器上电限流电阻功耗分析与优化

单相或三相交流电源供电的交直交变换器的前级电路为电压源AC-DC变换器,上电时需要限制冲击电流幅值,一般采用在功率线路中串联功率电阻的限流方法。通过分析不同阻值时电阻功耗的变化规律,提出了采用电阻电感组合和电阻变压器组合来降低上电功耗和抑制冲击电流峰值方法进行仿真分析。结果表明,在参数设计合理时,上述方法可以明显地降低单相交流电源供电时上电功耗和抑制冲击电流幅值,达到软上电功能。

一种一体化光纤声光调制器

该文采用光纤声光调制器集成化、低功耗和热仿真设计技术,设计并制作了工作波长1550 nm、光脉冲上升时间16.7 ns、光脉冲延时抖动1.5 ns、电功耗0.72 W(脉冲)、整体尺寸59.56 mm×49.48 mm×14.6 mm的高性能一体化光纤声光调制器。结果表明,该调制器具有体积小及功耗低等优点,对小型化低功耗光纤激光器、激光测风雷达及光纤分布式传感系统的研制有一定促进作用。

A Thermal-Conscious Integrated Circuit Power Model and Its Impact on Dynamic Voltage Scaling Techniques

We propose a novel thermal-conscious power model for integrated circuits that can accurately predict power and temperature under voltage scaling. Experimental results show that the leakage power consumption is underestimated by 52 % if thermal effects are omitted. Furthermore, an inconsistency arises when energy and temperature are simultaneously optimized by dynamic voltage scaling. Temperature is a limiting factor for future integrated circuits,and the thermal optimization approach can attain a temperature reduction of up to 12℃ with less than 1.8% energy penalty compared with the energy optimization one.

A Rapid RTL Power Estimator for Combinational Circuit

In order to estimate circuit power at the early design stage,a rapid analysis method is presented to calculate the RTL power of combinational modules.By building the power library with Monte Carlo simulation,the power dissipation of a certain module of any input vector can be obtained.This method uses Taylor's expansion to establish an equation based model.The simulation results for ISCAS85 circuit show that the method has error within 5%.

A 5mW 1.8V Low Over-Sampling Ratio ΣΔ Modulator with 81dB Dynamic Range

This work demonstrates that the ΣΔ modulator with a low oversampling ratio is a viable option for the high-resolution digitization in a low-voltage environment.Low power dissipation is achieved by designing a low-OSR modulator based on differential cascade architecture,while large signal swing maintained to achieve a high dynamic range in the low-voltage environment.Operating from a voltage supply of 1.8V,the sixth-order cascade modulator at a sampling frequency of 4-MHz with an OSR of 24 achieves a dynamic range of 81dB for a 80-kHz test signal,while dissipating only 5mW.

Designing Leakage-Tolerant and Noise-Immune Enhanced Low Power Wide OR Dominos in Sub-70nm CMOS Technologies

Two new circuit techniques to suppress leakage currents and enhance noise immunity while decreasing the active power are proposed. Eight-input OR gate circuits constructed with these techniques are simulated using 45nm BSIM4 SPICE models in HSPICE. The simulation results show that the proposed circuits effectively lower the active power, reduce the total leakage current, and enhance speed under similar noise immunity conditions. The active power of the two proposed circuits can be reduced by up to 8. 8% and 11.8% while enhancing the speed by 9.5% and 13.7% as compared to dual Vt domino OR gates with no gating stage. At the same time,the total leakage currents are also reduced by up to 80.8% and 82.4% ,respectively. Based on the simulation results,the state of the evaluation node is also discussed to reduce the total leakage currents of dual Vt dominos.

Synthesis Scheme for Low Power Designs Under Timing Constraints

To minimize the power consumption with resources operating at multiple voltages a time-constrained algorithm is presented.The input to the scheme is an unscheduled data flow graph (DFG),and timing or resource constraints.Partitioning is considered with scheduling in the proposed algorithm as multiple voltage design can lead to an increase in interconnection complexity at layout level.That is,in the proposed algorithm power consumption is first reduced by the scheduling step,and then the partitioning step takes over to decrease the interconnection complexity.The time-constrained algorithm has time complexity of O(n 2),where n is the number of nodes in the DFG.Experiments with a number of DSP benchmarks show that the proposed algorithm achieves the power reduction under timing constraints by an average of 46 5%.

A 71mW 8b 125MSample/s A/D Converter

A 1.8V 8b 125Msample/s pipelined A/D converter is presented.Power efficiency is optimized by size scaling down scheme using low power single stage cascode amplifier with a gain boosted structure.Global clock tree and local generators are employed to avoid loss and overlap of clock period.The ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 49.5dB(7.9ENOB) for an input of 62MHz at full speed of 125MHz,consuming only 71mW.It is implemented in 0.18μm CMOS technology with a core area of 0.45mm 2.

Design of an Analog Front End for Passive UHF RFID Transponder IC

This paper introduces a high-performance analog front end for a passive UHF RFID transponder IC, which is compatible with the ISO/IEC 18000-6B standard,operating at the 915MHz ISM band with a total supply current consumption less than 8μA. There are no external components, except for the antenna. The passive IC＇s power supply is taken from the energy of the received RF electromagnetic field with the help of a Schottky diode rectifier. The RFID analog front end includes a local oscillator, clock generator, power on reset circuit, matching network and backscatter,rectifier,regulator, and AM demodulator. The IC, whose reading distance is more than 3m,is fabricated with a Chartered 0.35μm two-poly four-metal CMOS process with Schottky diodes and is EEPROM supported. The core size is 300μm × 720μm.

An Ultra-Low-Power Embedded EEPROM for Passive RFID Tags

An ultra-low-power,256-bit EEPROM is designed and implemented in a Chartered 0.35μm EEPROM process. The read state power consumption is optimized using a new sense amplifier structure and an optimized control circuit. Block programming/erasing is achieved using an improved control circuit. An on silicon program/erase/read access time measurement design is given. For a power supply voltage of 1.8V,an average power consumption of 68 and 0.6μA for the program/erase and read operations,respectively,can be achieved at 640kHz.

A Novel Charge-Transfer Matching Cell for High-Precision Correlation and Low-Power

A novel matching cell circuitry using charge transfer circuit technique for high precision correlation calculation is presented.The cell calculates the absolute value of the difference between two analog input voltages and amplifies the result.Amplification gain can be designed by the capacitance size in the cell and threshold voltage mismatch can be canceled automatically,thus high precision operation of the circuit is achieved.The circuit can be operated with low power dissipation of about 12μW at a frequency of 50MHz.Because of its simple structure and small silicon area,the matching cell is suitable to realize the correlation dealing with many template vectors that have many elements in a chip.

Application study of dynamic voltage scaling policies

Based on the fundamental relationship among the circuit power, the circuit delay and the supply voltage, four theorems associated with the application of dynamic voltage scaling （DVS） policies are proposed and proved. First, the existence characteristics of the optimal supply voltage for a single task are proved, which suggests that the optimal supply voltage for the single task should be selected only within a one-dimensional term, and the corresponding task end time by the optimal supply voltage should be identical with its deadline. Then, it is pointed out that the minimum energy consumption that the DVS policy can obtain when completing a single task is certainly lower than that of the dynamic power management （DPM） policy or the combined DVS＋DPM policy under the same conditions. Finally, the theorem of energy consumption minimization for a multi-task group is proposed, which declares that it is necessary to keep the processor in the execution state during the whole task period to obtain the minimum energy consumption, while satisfying the deadline constraints of any task.

Analysis and Design of a Low-Cost RFID Tag Analog Front-End

A new,low-cost RFID tag analog front-end compatible with ISO 14443A and ISO 14443B is presented. By substituting conventional multi-circle antenna with single-circle antenna, the package cost of the tag is greatly reduced. Based on this exasperate antenna performance,a new rectifier with high power conversion efficiency and low turn-on voltage is presented. The circuit is implemented in an SMIC 0.18μm EEPROM process. Measurement results show that with a 120kΩ load,the power conversion efficiency reaches as high as 36%. For a sinusoidal wave with magnitude of 0. 5V, the output DC voltage reaches IV,which is high enough for RFID tags. The read distance is as far as 22cm.

A Slice Analysis-Based Bayesian Inference Dynamic Power Model for CMOS Combinational Circuits

To improve the accuracy and speed in cycle-accurate power estimation, this paper uses multiple dimensional coefficients to build a Bayesian inference dynamic power model. By analyzing the power distribution and internal node state, we find the deficiency of only using port information. Then, we define the gate level number computing method and the concept of slice, and propose using slice analysis to distill switching density as coefficients in a special circuit stage and participate in Bayesian inference with port information. Experiments show that this method can reduce the power-per-cycle estimation error by 21.9% and the root mean square error by 25.0% compared with the original model, and maintain a 700 ＋ speedup compared with the existing gate-level power analysis technique.

A Low Voltage,Low Power RF/Analog Front-End Circuit for Passive UHF RFID Tags

This paper presents a low voltage, low power RF/analog front-end circuit for passive ultra high frequency （UHF） radio frequency identification （RFID） tags. Temperature compensation is achieved by a reference generator using sub-threshold techniques. The chip maintains a steady system clock in a temperature range from - 40 to 100℃. Some novel building blocks are developed to save system power consumption,including a zero static current power-on reset circuit and a voltage regulator. The RF/analog front-end circuit is implemented with digital base-band and EEPROM to construct a whole tag chip in 0. 18μm CMOS EEPROM technology without Schottcky diodes. Measured results show that the chip has a minimum supply voltage requirement of 0.75V. At this voltage, the total current consumption of the RF/analog frontend circuit is 4.6μA.

A 1V,156.7μW,65.9dB Rail-to-Rail Operational Amplifier by Means of Negative Resistance Load and Replica-Amplifier Gain Enhancement

A low-voltage, low-power, and high-gain rail-to-rail operational amplifier （OpAmp） is presented. The replica-amplifier gain enhancement technique is applied to improve the DC gain of the amplifier, which does not degrade the output swing and is very suitable for low-voltage applications. In a 0. 18/μm standard CMOS process,a 1V OpAmp with rail-to-rail output is designed. For a load capacitance of 5 pF,simulation by HSPICE shows that this OpAmp achieves an effective open-loop DC gain of 65. 9dB,gain bandwidth of 70.28 MHz,and phase margin of 50 with a quiescent power dissipation of 156.7μW.

Energy-efficient data transmission with non-ideal circuit power for downlink cellular networks

The downlink energy-efficient transmission schedule with non-ideal circuit power over Wreless networks involving a single transmitter and multiple receivers was investigated. According to the special structure of the problem, a novel algorithm called OOSCPMR （the optimal offine scheduling with non-ideal circuit power for multi-receivers） is proposed, and the optimal offine solutions to optimize the energy- efficient transmission policy are found. The packets to be transmitted can be divided into two types where one type of packet is determined to be transmitted using the enrgy- efficient tansmission time, and the other type of packet is determined by the ID moveright algorithm. Finally, an energy-efficient online schedule is developed based on te proposed OOSCPMR algoriAm. Simulation results show that the optima offline transmission schedule provides te lower bound performance for the online tansmission schedule. The proposed optimal offline and online policy is more energy efficient than the existing schemes tat assume ideal circuit power.

A Novel Power Supply Solution of a Passive RFID Transponder

This paper presents a power supply solution for fully integrated passive radio-frequency identification （RFID） transponder IC, which has been implemented in 0.35μm CMOS technology with embedded EEPROM from Chartered Semiconductor. The proposed AC/DC and DC/DC charge pumps can generate stable output for RFID applications with quite low power dissipation and extremely high pumping efficiency. An analytical model of the voltage multiplier, comparison with other charge pumps, simulation results, and chip testing results are presented.

Function electrical stimulation circuit for neural signal regeneration system

A low-power, high-gain circuit for function electrical stimulation （FES） is designed for the microelectronic neural signal regeneration system based on CSMC （CSMC Technologies Corporation） 0. 6μm CMOS （complementary metal-oxide-semiconductor transistor） technology. It can be used to stimulate microelectrodes connected with the nerve bundles to regenerate neural signals. This circuit consists of two stages： a full differential folded-cascode amplifier input stage and a complementary class-AB output stage with an overload protection circuit. The rail-to-rail input and output stages are used to ensure a wide range of input and output voltages. The simulation results show that the gain of the circuit is 81 dB; the 3 dB-bandwidth is 295 kHz. The chip occupies a die area of 1.06 mm × 0. 52 mm. The on-wafer measurement results show that under a single supply voltage of ＋ 5 V, the DC power consumption is about 7. 5 mW and the output voltage amplitude is 4. 8 V. The chip can also mn well under single supply voltage of ＋ 3.3 V.