A fast-locking, low-jitter, phase-locked loop （PLL） with a simple phase-frequency detector is proposed. The phase-frequency detector is composed of only two XOR gates. It simultaneously achieves low jitter and short...A fast-locking, low-jitter, phase-locked loop （PLL） with a simple phase-frequency detector is proposed. The phase-frequency detector is composed of only two XOR gates. It simultaneously achieves low jitter and short locking time. The voltage-controlled oscillator within the PLL consists of four-stage ring oscillators which are coupled to each other and oscillate with the same frequency and a phase shift of 45. The PLL is fabricated in 0. 1Stem CMOS technology. The measured phase noise of the PLL output at 500kHz offset from the 5GHz center frequency is - 102.6dBc/Hz. The circuit exhibits a capture range of 280MHz and a low RMS jitter of 2.06ps. The power dissipation excluding the output buffers is only 21.6roW at a 1.8V supply.展开更多
Tail buffeting at high angle of attack causes distinct fatigue problem on tail structure of twin tail fighters.In this study,a piezoelectric active control experiment of tail buffeting was performed in a wind tunnel u...Tail buffeting at high angle of attack causes distinct fatigue problem on tail structure of twin tail fighters.In this study,a piezoelectric active control experiment of tail buffeting was performed in a wind tunnel using arching PZT actuator(APA) and principal modal control(PMC) method.Test results showed the peak value of power spectral density(PSD) function of tail buffeting acceleration response could be suppressed by about 42% when the angle of attack reached 35°,indicating the validity and feasibility of PMC method and APA for tail buffeting alleviation at high angle of attack.展开更多
文摘A fast-locking, low-jitter, phase-locked loop （PLL） with a simple phase-frequency detector is proposed. The phase-frequency detector is composed of only two XOR gates. It simultaneously achieves low jitter and short locking time. The voltage-controlled oscillator within the PLL consists of four-stage ring oscillators which are coupled to each other and oscillate with the same frequency and a phase shift of 45. The PLL is fabricated in 0. 1Stem CMOS technology. The measured phase noise of the PLL output at 500kHz offset from the 5GHz center frequency is - 102.6dBc/Hz. The circuit exhibits a capture range of 280MHz and a low RMS jitter of 2.06ps. The power dissipation excluding the output buffers is only 21.6roW at a 1.8V supply.
基金supported by the National Natural Science Foundation of China (Grant No. 11072198)the Basic Research Program of Northwestern Polytechnical University (Grant No. JC201102) "111" Project(Grant No. B07050)
文摘Tail buffeting at high angle of attack causes distinct fatigue problem on tail structure of twin tail fighters.In this study,a piezoelectric active control experiment of tail buffeting was performed in a wind tunnel using arching PZT actuator(APA) and principal modal control(PMC) method.Test results showed the peak value of power spectral density(PSD) function of tail buffeting acceleration response could be suppressed by about 42% when the angle of attack reached 35°,indicating the validity and feasibility of PMC method and APA for tail buffeting alleviation at high angle of attack.
